Wafer Analysis System Using Virtual Copying for Yield Inspection
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Solution Overview
Problem
Existing wafer analyzing devices face challenges in accurately inspecting and analyzing all areas of multiple wafers, which hinders the precise analysis of semiconductor yield and defect causes.
Innovation Solution
A wafer analyzing device and system that includes an analysis value acquiring module to measure analysis values from a first wafer and a second wafer, and an analysis value calculating module to classify remaining unit areas in the second wafer, calculate estimated analysis values using measured values from the first and second wafers, and identify defect causes through correlation analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If inspections are performed on all areas of multiple wafers to ensure analysis accuracy, then measurement precision is improved, but device complexity and inspection time increase
Solution Approach 1:
The patent uses a copying approach by creating a virtual replica of the wafer map. Instead of physically inspecting all areas of multiple wafers, the system copies the spatial relationship and defect distribution patterns from a first wafer to generate estimated analysis values for a second wafer. This virtual copying allows accurate analysis without performing all physical inspections.
Solution Approach 2:
The patent applies preliminary action by performing inspections on a subset of areas (first wafer and reference areas of second wafer) before using those results to estimate values for remaining areas. The inspection of reference unit areas in the second wafer serves as preliminary data collection that enables subsequent estimation without requiring complete inspection of all wafer areas.
2Measurement precision
If inspections are performed on all areas of multiple wafers to ensure analysis accuracy, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The system creates a virtual copy of the wafer inspection data structure, allowing estimation of analysis values for uninspected areas by copying and adapting patterns from inspected areas. This eliminates the time-consuming requirement to physically inspect every area while maintaining analysis accuracy through pattern-based estimation.
Solution Approach 2:
The patent applies partial action by inspecting only a subset of areas (N>K areas where K reference areas are selected) rather than all areas. By strategically selecting reference unit areas that represent the overall defect distribution pattern, the system achieves accurate analysis with reduced inspection time and fewer measured areas.
3Measurement precision
If all unit areas are inspected to analyze defect distribution, then measurement precision is improved, but productivity decreases
Solution Approach 1:
The system copies defect distribution patterns from inspected reference areas to estimate defect characteristics across all wafer areas. This virtual copying enables precise defect analysis without the productivity loss associated with complete physical inspection of every unit area on every wafer.
Solution Approach 2:
The patent implements partial inspection by measuring only K reference unit areas out of N total unit areas (where K<N). This partial action approach maintains sufficient defect distribution representation for accurate analysis while significantly improving inspection efficiency and productivity.
4Reliability
If multiple wafers are inspected to analyze yield and defects, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent creates a universal inspection framework that can analyze multiple wafers using the same reference-based estimation approach. The system uses a universal mapping between first wafer data and second wafer reference areas, allowing reliable multi-wafer analysis without increasing device complexity through standardized processing.
Solution Approach 2:
The system copies the analytical framework and reference data structure across multiple wafers, enabling reliable yield and defect analysis through consistent pattern recognition. This copying approach maintains reliability across multiple samples while avoiding the complexity of developing separate analysis methods for each wafer.
Data Source
AI summary
A semiconductor wafer analyzing device and semiconductor wafer analyzing system are disclosed that provide estimated analysis values of unit areas that are not measured in a target wafer. The device and system calculate estimated analysis values based on measured analysis values of unit areas in a basic wafer and measured analysis values of some unit areas in the target wafer.