Semiconductor Wafer Backside Alignment Using Frontside Marks
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Solution Overview
Problem
Conventional methods for fabricating semiconductor devices with super junction metal-oxide-semiconductor field-effect transistors (SJ-MOSFET) and reverse conducting insulated-gate bipolar transistors (RC-IGBT) suffer from large alignment errors (30 microns) between backside and frontside patterns due to the silicon wafer being faced down during the backside patterning process.
Innovation Solution
The method involves forming frontside alignment marks distanced from the circumference of the semiconductor wafer, using multiple epitaxial layers and intermediate alignment marks, and employing advanced alignment tools to achieve sub-micron precision alignment, integrating RC-IGBT and SJ-MOSFET on a common substrate, and applying a singulation process to form precise semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a notch on the silicon wafer is used for alignment, then the backside patterning process can be performed, but large alignment errors (30 microns) occur between backside and frontside patterns
Solution Approach 1:
The patent introduces intermediate alignment marks formed in the frontside epitaxial layer as mediators between the frontside and backside patterns. These intermediate marks serve as reference points that can be precisely aligned with both the frontside alignment marks and the backside pattern, eliminating the need to directly align the backside pattern with distant frontside marks while the wafer is face down.
Solution Approach 2:
The patent creates a multi-layer alignment structure by forming intermediate alignment marks within the epitaxial layer thickness dimension. This vertical dimensionality allows the alignment system to reference frontside marks at different depths, improving horizontal alignment precision without being constrained by the traditional single-plane alignment approach.
2Manufacturing precision
If alignment marks are placed far from the wafer circumference, then alignment accuracy improves to 0.5 microns, but the complexity of the fabrication process increases
Solution Approach 1:
The patent performs preliminary actions by forming multiple epitaxial layers with embedded alignment marks during the frontside fabrication process, before the wafer is flipped for backside patterning. This preliminary preparation of the alignment reference structure eliminates the need for complex real-time alignment adjustments during backside processing.
Solution Approach 2:
The patent segments the alignment function into multiple components: frontside alignment marks, intermediate alignment marks embedded in epitaxial layers, and backside pattern alignment. This segmentation allows each alignment stage to be optimized independently, achieving high overall precision without requiring a single overly complex alignment mechanism.
Data Source
AI summary
A method comprises the steps of providing a semiconductor wafer comprising a substrate layer; forming a first alignment mark and a second alignment mark; forming a plurality of super junction buffer regions; forming additional two or more epitaxial layers; forming additional one or more alignment marks; forming a top layer; thinning the wafer; forming a first plurality of regions and a second plurality of regions; and applying a singulation process. Devices made by the method have reduced misalignment, between a top portion and a bottom portion of an interface within the devices, for less than 0.5 micron.