Semiconductor Wafer Backside Crack Division for Stress Isolation
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Solution Overview
Problem
The scribing and breaking method for semiconductor wafer division can lead to residual stress near the surface where element structures are formed, causing chipping or unintended cracks, which degrade the reliability of semiconductor devices during repeated operations.
Innovation Solution
A manufacturing method that forms a crack in the semiconductor wafer's thickness direction along the boundary between adjacent element structures by pressing a scribing member against the wafer's second surface, allowing the wafer to be divided by a breaking member on the first surface side, thereby isolating residual stress away from the element structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a scribing and breaking method is used to divide the semiconductor wafer, then the manufacturing process is simplified and productivity is improved, but residual stress is generated near the element structures causing chipping or unintended cracks
Solution Approach 1:
The wafer division process is segmented into two distinct stages: first forming a crack along the boundary by pressing from the second surface, then dividing by pressing from the first surface. This segmentation allows residual stress to be localized in the crack region away from element structures, maintaining both productivity and reliability
Solution Approach 2:
A crack is formed in advance along the boundary between element structures before the actual division occurs. This preliminary crack formation directs the subsequent breaking action and isolates residual stress to the crack region, preventing stress-induced damage to element structures while enabling efficient division
2Manufacturing precision
If pressing is applied to form a crack along the boundary, then the wafer can be divided with minimal material removal, but residual stress concentrates near the surface causing chipping
Solution Approach 1:
Instead of pressing from the first surface (where element structures are located) to form the crack, the method inverts the approach by pressing from the second surface. This inversion directs residual stress away from element structures, achieving precise division without stress-induced chipping
Solution Approach 2:
Residual stress is localized to the crack region along the boundary between element structures, rather than being distributed across the entire wafer surface. This localized stress concentration occurs away from element structures, preventing harmful effects while maintaining division precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the likelihood of performance degradation due to residual stress, as the stress is localized to the second surface opposite to the element structures, minimizing the impact of chipping or cracking on the semiconductor device's reliability.
Implementation Method 1
forming a crack extending in a thickness direction of the semiconductor wafer along a boundary between adjacent element structures by pressing a pressing member against a second surface of the semiconductor wafer
Implementation Method 2
dividing the semiconductor wafer along the boundary by pressing a dividing member against the semiconductor wafer on a first surface side along the boundary
Data Source
AI summary
A manufacturing method of a semiconductor device includes: forming a plurality of element structures in a form of matrix on a first surface of a semiconductor wafer; forming a crack extending in a thickness direction of the semiconductor wafer along a boundary between the element structures adjacent to each other by pressing a pressing member against a second surface of the semiconductor wafer opposite to the first surface along the boundary; and dividing the semiconductor wafer along the boundary by pressing a dividing member against the semiconductor wafer on a first surface side along the boundary.