Thermally Conductive Wafer Backside Layer to Limit Warpage

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Solution Overview

Problem

Existing semiconductor device fabrication methods face challenges in effectively managing localized heat generated by high power consumption, which can lead to substrate warping or destructive chemical reactions due to inadequate thermal conduction.

Innovation Solution

A thermally conductive surface layer is created on semiconductor wafers using a combination of metallic nanoparticles and graphene, where metallic nanoparticles embedded with carbon species are deposited and sintered to form a graphene sheet, enhancing thermal conductivity while minimizing wafer warpage and stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If a traditional metal layer is deposited on the wafer backside to improve thermal conduction, then heat dissipation is enhanced, but the fabrication process becomes complex and time-consuming

Engineering Contradiction:
Improveheat dissipationVSAvoidfabrication process time
Core Design Contradiction:
TemperatureVSProductivity

Solution Approach 1:

The patent uses composite materials consisting of metallic nanoparticles (such as copper, aluminum, or silver) combined with carbon species (such as graphite or amorphous carbon). This composite structure provides high thermal conductivity while enabling direct deposition onto the wafer backside, eliminating complex multi-step fabrication processes and significantly reducing manufacturing time.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent changes the physical state and form of the thermal conduction material from bulk metal layers to nanoparticle suspensions that can be directly deposited and sintered. This parameter change from traditional metal deposition to nanoparticle-based thermal interface material enables a simplified, single-step fabrication process that maintains high thermal conductivity.

Inventive Principle:
Principle #35Parameter changes

2Power

If high power consumption devices are integrated on the wafer, then device functionality is improved, but localized heat generation causes substrate warping and destructive chemical reactions

Engineering Contradiction:
Improvedevice power consumptionVSAvoidsubstrate warping and chemical reactions
Core Design Contradiction:
PowerVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a thermal interface material comprising metallic nanoparticles and carbon species as an intermediary layer between the high power consumption devices and the wafer substrate. This intermediary material acts as a thermal conduit that efficiently transfers localized heat away from sensitive device regions, preventing substrate warping and destructive chemical reactions while allowing high power devices to function.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces traditional mechanical thermal management approaches (such as heat sinks attached to the backside) with a nanoscale thermal conduction layer that provides direct thermal pathways at the device level. This substitution enables more effective heat management at the source, preventing localized thermal damage before it can affect the substrate.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Temperature

If a thick metal layer is used to improve thermal conduction, then heat dissipation is enhanced, but wafer stress and warpage increase

Engineering Contradiction:
Improvethermal conductivityVSAvoidwafer warpage
Core Design Contradiction:
TemperatureVSShape

Solution Approach 1:

The patent applies local quality by using nanoparticle-based thermal interface material that can be selectively deposited only in regions requiring enhanced thermal conduction, rather than covering the entire wafer backside with a thick metal layer. This localized application provides targeted heat dissipation while minimizing overall wafer stress and preventing warpage.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses a thin film of nanoparticle-based thermal interface material instead of a thick metal layer. This thin film structure provides sufficient thermal conductivity to manage heat effectively while being flexible enough to conform to the wafer surface without inducing significant stress or warpage.

Inventive Principle:
Principle #30Flexible shells and thin films

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively delocalizes heat, reducing wafer warpage and stress by providing a thin, high thermal conductivity backside layer that maintains the integrity of previously fabricated circuits, thus improving heat dissipation without damaging the device components.

Implementation Method 1

metallic nanoparticles embedded with carbon species are deposited and sintered to form a graphene sheet

Methodology Applied
Scientific EffectSintering: Sintering

Implementation Method 2

enhancing thermal conductivity while minimizing wafer warpage and stress

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 3

The conductive metal layer 208 spreads heat across the span of the wafer 202, delocalizing elevated temperatures and facilitating heat dissipation

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 4

providing a thin, high thermal conductivity backside layer that maintains the integrity of previously fabricated circuits

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20240153841A1Thermally conductive wafer layer
Publication Date: 2024.05.09 TEXAS INSTRUMENTS INC
  • US20240153841A1 patent drawing
  • US20240153841A1 patent drawing
  • US20240153841A1 patent drawing

AI summary

In described examples, a method comprises forming a patterned region on a first surface of the semiconductor substrate. The method also comprises forming circuitry in the patterned region. The method further comprises forming a metallic layer on a second surface of the semiconductor substrate, in which the second surface opposes the first surface; and forming a carbon layer on the metallic layer.