Wafer Backside Symmetrical Patterning for Precise Planarization
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Solution Overview
Problem
Existing semiconductor wafer manufacturing processes suffer from incomplete planarization of layers, leading to rough surfaces and affecting the quality of the wafers.
Innovation Solution
A planarization method involving the formation of a symmetrical pattern mask on the wafer backside, followed by a wet etching process and chemical mechanical planarization to remove protection layers and symmetrical patterns, using etchants like HNO3, H2SO4, and HF, and employing polishing machines with grind pads and slurry to achieve planarity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional planarization methods are used, then the manufacturing process is simple, but the wafer surface planarity is poor
Solution Approach 1:
A symmetrical pattern is formed on the backside of the wafer before the planarization process. This preliminary action creates a structural feature that enables effective suction mounting during CMP, allowing the wafer to be securely held and planarized with high precision. The pattern formation includes depositing a sacrificial layer, forming a mask pattern, and etching the symmetrical structure that will later serve as the mounting interface.
Solution Approach 2:
The symmetrical pattern on the wafer backside acts as an intermediary element that mediates between the wafer and the CMP suction mounting system. This pattern provides a controlled interface for vacuum suction, ensuring the wafer is properly positioned and held flat during the planarization process, thereby achieving high manufacturing precision without requiring direct suction on the wafer surface itself.
2Manufacturing precision
If the backside of the wafer is etched to form a symmetrical pattern, then the planarity is improved, but the process steps increase
Solution Approach 1:
The planarization process is segmented into distinct phases: first forming the symmetrical pattern on the backside, then using that pattern for suction mounting during CMP. This segmentation allows each step to be optimized independently - the pattern formation uses standard deposition and etching processes, while the CMP step benefits from the pre-prepared suction interface, ultimately improving overall manufacturing efficiency despite the additional pattern formation step.
Solution Approach 2:
The invention changes the physical and chemical parameters of the wafer backside by forming a symmetrical pattern with specific geometric characteristics. This parameter change creates a surface structure that optimizes vacuum suction adhesion during CMP, allowing the planarization process to achieve high precision while maintaining reasonable productivity through controlled parameter optimization rather than excessive process steps.
3Measurement precision
If a pattern mask is formed on the back surface, then the etching precision is improved, but the device complexity increases
Solution Approach 1:
While the overall pattern is symmetrical, the mask formation process uses asymmetric photolithography techniques to define the precise boundaries of the symmetrical features. This approach achieves high etching precision by using asymmetric mask alignment and exposure methods, then translating that precision into a symmetrical final pattern that provides balanced suction characteristics during CMP mounting.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly improves wafer planarity and flatness, reducing wafer warp and enhancing topography, while protecting the semiconductor structure from etching damage.
Implementation Method 1
The outward exposed portion and the inward exposed portion of the wafer are etched to form a symmetrical pattern in a backside of the wafer. A planarization process is performed to remove the protection layer on the front surface of the wafer and the symmetrical pattern in the backside of the wafer
Implementation Method 2
the wafer is mounted on a polishing machine with a grind pad through sucking the symmetrical pattern in the backside of the wafer, and the protection layer on the semiconductor structure is removed
Data Source
AI summary
Embodiments of this disclosure provide a planarization method of a wafer, and the method includes the following steps. A wafer with a semiconductor structure on a front surface of the wafer is provided. A protection layer is formed on the semiconductor structure of the wafer. A pattern mask is formed on a back surface of the wafer to cover a first portion of the back surface and expose a second portion and a third portion of the back surface. Also, the pattern mask is a symmetrical shape. The second portion and the third portion of the wafer are etched to form a symmetrical pattern in a backside of the wafer. A planarization process is performed to remove the protection layer on the front surface of the wafer.