Semiconductor Wafer Backside Security Marking for Trusted Fabrication
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Solution Overview
Problem
The use of untrusted foundries for semiconductor chip manufacturing poses security concerns, as chip customers cannot control or monitor the manufacturing process, leading to potential counterfeiting, reverse engineering, and the introduction of malicious features in semiconductor chips.
Innovation Solution
A method involving the formation of security marks on semiconductor wafers by implanting inert species on their backside, allowing for verification of the wafer's authenticity and integrity through pattern matching and marking inspection, ensuring the wafer has not been compromised during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If untrusted foundries are used for semiconductor chip manufacturing, then chip production capabilities are expanded and customer choices are increased, but security risks increase including counterfeiting, reverse engineering, and introduction of malicious features
Solution Approach 1:
Security marks are formed on the semiconductor wafer during the fabrication process at trusted locations before the wafer leaves the controlled environment. This preliminary marking ensures that even when the wafer is processed at untrusted foundries, its authenticity can be verified later through inspection of these pre-established security features
Solution Approach 2:
The system implements a feedback mechanism where security marks are formed during fabrication, recorded in a database with their expected locations and characteristics, and then verified through inspection at later stages. This closed-loop feedback ensures that any deviations or tampering can be detected, maintaining reliability even when using untrusted foundries
2Reliability
If security marks are formed by implanting inert species on the backside of semiconductor wafers, then wafer authentication and integrity verification are improved, but manufacturing process complexity increases
Solution Approach 1:
The security marking process leverages existing semiconductor fabrication equipment and processes. The inert species implantation uses standard ion implantation tools already present in fabrication facilities, and the marks are formed as part of the normal manufacturing flow without requiring separate dedicated marking equipment, thus avoiding significant increases in manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides a secure and reliable means to authenticate semiconductor wafers, preventing unauthorized changes and ensuring the integrity of the manufacturing process, even when using untrusted foundries, by embedding and verifying security marks on the wafers.
Implementation Method 1
At least one security mark is formed at one or more locations embedded within a backside of the semiconductor wafer by implanting an inert species at the one or more locations
Data Source
AI summary
A method for securing and verifying semiconductor wafers during fabrication includes receiving a semiconductor wafer after a layer of features has been patterned thereon. At least one security mark is formed at one or more locations embedded within a backside of the semiconductor wafer by implanting an inert species at the one or more locations. At a subsequent point in fabrication and/or after fabrication of the semiconductor wafer has completed the backside of the wafer is inspected for detection of the at least one security mark. If the at least one security mark is not detected at an expected location within the backside of the semiconductor wafer a determination is made that the semiconductor wafer has been compromised.