Wafer-Level Biosensor Packaging With TSVs for Faster Data Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Biosensors face limitations in data transfer rates and power consumption due to the physical distance between the biosensor chip and the DRAM chip on a printed circuit board, leading to increased resistance, capacitance, and inductance in the signal path, which affects bandwidth and accuracy.
Innovation Solution
The implementation of wafer-level packaging to integrate a biosensor with a microfluidic channel cap structure using a CMOS-compatible process flow, reducing the signal path resistance, capacitance, and inductance through through-silicon via (TSV) interfacing between chips, thereby minimizing power consumption and noise while increasing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If biosensor chip and DRAM chip are placed on a printed circuit board, then device complexity is reduced and ease of manufacture is improved, but signal path resistance, capacitance, and inductance increase leading to decreased data transfer rates and increased power consumption
Solution Approach 1:
The patent merges the biosensor chip and DRAM chip into a single integrated wafer-level package, eliminating the need for separate printed circuit board mounting. This integration reduces the physical distance between components, thereby decreasing signal path resistance, capacitance, and inductance, which directly reduces power consumption while maintaining ease of manufacture through standardized packaging processes.
Solution Approach 2:
The patent transitions from a planar two-chip arrangement on a PCB to a three-dimensional stacked architecture within a single wafer package. By utilizing vertical stacking and through-silicon vias, the signal path is shortened from horizontal traversal across the board to vertical connections within the package, reducing electromagnetic interference and power consumption while preserving manufacturing simplicity.
2Ease of manufacture
If biosensor chip and DRAM chip are placed on a printed circuit board, then device complexity is reduced and ease of manufacture is improved, but physical distance increases leading to decreased data transfer rates
Solution Approach 1:
The patent combines the biosensor chip and DRAM chip into a single integrated package, reducing the physical separation between components. This merger shortens the signal transmission path, thereby increasing data transfer rates while maintaining ease of manufacture through established wafer-level packaging techniques and standardized interface protocols.
Solution Approach 2:
The patent employs a three-dimensional stacked architecture with through-silicon vias to establish vertical electrical connections between the biosensor chip and DRAM chip. This dimensional transition reduces the signal path length from horizontal traversal across the printed circuit board to direct vertical connections within the package, significantly increasing data transfer rates while preserving manufacturing simplicity.
3Speed
If wafer-level packaging with TSV interfacing is implemented, then data transfer rates increase and power consumption decreases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the integrated package into distinct functional layers: the biosensor chip layer, the through-silicon via interconnect layer, and the DRAM chip layer. This segmentation allows each layer to be optimized independently while maintaining overall integration benefits, thereby increasing data transfer rates without proportionally increasing device complexity.
Solution Approach 2:
The patent introduces through-silicon vias as intermediary conductive structures that facilitate electrical connections between the biosensor chip and DRAM chip. These vias act as mediators that enable high-speed data transfer while consolidating multiple connection functions into a single integrated structure, thereby increasing performance without proportionally increasing overall device complexity.
4Speed
If wafer-level packaging with TSV interfacing is implemented, then data transfer rates increase and power consumption decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary alignment and bonding of the biosensor chip and DRAM chip during the wafer-level packaging process, before final package assembly. This preliminary action ensures precise registration of through-silicon vias with corresponding pads on both chips, achieving the required manufacturing precision for high-speed data transfer while streamlining the overall fabrication process.
Solution Approach 2:
The patent optimizes critical manufacturing parameters including via diameter, via depth, bonding temperature, and bonding pressure to achieve the required precision for TSV interfacing. By carefully controlling these parameters within specified ranges, the patent achieves high manufacturing precision for the integrated package while maintaining data transfer rate improvements and power consumption reductions.
Data Source
AI summary
A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; a carrier substrate on the MLI structure; a first through substrate via (TSV) structure extending though the carrier substrate and configured to provide an electrical connection between the MLI structure and a separate die; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; and a microfluidic channel cap structure attached to the buried oxide layer.