Wafer-Level Biosensor Packaging With TSVs for High-Bandwidth Readout
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current biosensor systems face limitations in data transfer rates and power consumption due to the physical distance between biosensor chips and dynamic random-access memory (DRAM) chips on a printed circuit board, leading to increased resistance, capacitance, and inductance in the signal path, which affects bandwidth and introduces noise and distortion.
Innovation Solution
The implementation of wafer-level packaging to integrate biosensors with a microfluidic channel cap structure using a complementary metal-oxide-semiconductor (CMOS) compatible process flow, reducing the signal path resistance, capacitance, and inductance through through silicon via (TSV) interfacing between chips, thereby minimizing power consumption and noise while increasing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If biosensor chips and DRAM chips are placed on a printed circuit board with physical distance between them, then device complexity is reduced and ease of manufacture is improved, but signal path resistance, capacitance, and inductance increase leading to reduced bandwidth and increased noise
Solution Approach 1:
The patent merges the biosensor chip and DRAM chip into a single integrated package structure, eliminating the need for separate printed circuit board mounting and inter-chip connections. This integration directly reduces signal path resistance, capacitance, and inductance while maintaining manufacturing feasibility through standardized packaging processes.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout on a printed circuit board to a three-dimensional stacked architecture where biosensor and DRAM chips are vertically arranged and connected through through-silicon vias. This dimensional change dramatically shortens the signal path length while preserving ease of manufacture through established 3D integration techniques.
2Productivity
If physical distance between biosensor and DRAM chips is reduced through integration, then bandwidth is increased and noise is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent performs preliminary integration of the biosensor chip and DRAM chip into a unified package structure before final assembly. Through-silicon via connections are pre-established during the packaging process, and microfluidic channels are pre-formed to deliver samples directly to the biosensor. This preliminary integration maximizes data transfer rate while controlling complexity through modular design.
Solution Approach 2:
The patent introduces a carrier substrate as an intermediary component that holds both the biosensor chip and DRAM chip in close proximity. This carrier substrate provides mechanical support and electrical interconnection through standardized interfaces, enabling high-speed data transfer while simplifying the overall manufacturing process through a single integrated assembly unit.
3Loss of energy
If through silicon via interfacing is implemented to reduce signal path length, then power consumption is reduced and bandwidth is increased, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the physical parameters of the through-silicon via structure, including via diameter, depth, and spacing, to achieve the best balance between power consumption reduction and manufacturing feasibility. By carefully controlling these parameters within standardized ranges, the patent minimizes power loss while maintaining compatibility with existing manufacturing capabilities and reducing precision requirements.
Data Source
AI summary
A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; a carrier substrate on the MLI structure; a first through substrate via (TSV) structure extending though the carrier substrate and configured to provide an electrical connection between the MLI structure and a separate die; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; and a microfluidic channel cap structure attached to the buried oxide layer.