Wafer-Bonded 3D Memory Interface for High-Bandwidth Embedded Access
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Solution Overview
Problem
Conventional DRAM arrays have lower density and capacity due to their two-dimensional structure on planar semiconductor substrates, sharing precious silicon real estate with support circuitry, and face limitations in bandwidth and power efficiency in signal transmission across wire-bonded circuits.
Innovation Solution
The integration of a high-bandwidth, high-capacity memory system using wafer bonding techniques, such as flip-chip or TSV, to stack semiconductor dies with three-dimensional arrays of storage transistors, allowing for low-power, low-latency communication across conductive posts and enabling a large embedded memory interface with tens of thousands of simultaneous bit transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional DRAM arrays are formed on planar semiconductor substrates, then manufacturing process is simple, but memory density and capacity are limited due to two-dimensional structure sharing silicon real estate with support circuitry
Solution Approach 1:
The patent transitions from two-dimensional planar DRAM arrays to three-dimensional stacked memory structures by bonding multiple semiconductor dies vertically. This dimensional change allows memory cells to be arranged in three dimensions, dramatically increasing memory capacity while maintaining manufacturing simplicity through standard wafer bonding processes.
2Device complexity
If wire-bonded circuits are used for signal transmission, then device complexity is low, but bandwidth and power efficiency are limited
Solution Approach 1:
The patent removes the wire-bonding interconnection layer by forming direct conductive posts through the bonded semiconductor dies. This extraction of the wire-bonding step eliminates the bandwidth and power efficiency limitations of wire-bonded circuits while reducing overall device complexity through direct electrical contact between stacked dies.
3Ease of manufacture
If wire-bonded circuits are used for signal transmission, then manufacturing process is conventional, but power consumption is high and latency is increased
Solution Approach 1:
The patent replaces the mechanical wire-bonding process with direct conductive post formation through wafer bonding. This substitution eliminates the long signal paths and high capacitance of wire-bonded connections, dramatically reducing power consumption and latency while maintaining manufacturing feasibility through established semiconductor bonding techniques.
4Ease of manufacture
If two-dimensional DRAM structure is used, then fabrication is straightforward, but silicon real estate is wasted due to sharing with support circuitry
Solution Approach 1:
The patent vertically stacks multiple semiconductor dies to create three-dimensional memory structures, freeing up the two-dimensional silicon real estate on each die for memory cell arrays. Support circuitry can be placed on separate dies or on the same die without competing for the same silicon area, thereby maximizing silicon real estate utilization while keeping fabrication straightforward through standard wafer bonding.
Data Source
AI summary
An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.