Wafer-Bonded 3D Memory and Logic for High-Bandwidth Access
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Solution Overview
Problem
Conventional DRAM arrays are limited by their 2-dimensional structure, sharing silicon real estate with support circuitry, leading to lower density and capacity compared to 3-D NOR memory arrays, and face bandwidth limitations due to pin constraints and high power/latency in signal transmission.
Innovation Solution
A high-bandwidth, high-capacity memory device is created by wafer-bonding a memory circuit with a logic circuit, using techniques like flip-chip, TSV, silicon interposer, or silicon bridge, enabling modular, independently addressable memory segments with low-capacitance studs for low-power, high-bandwidth communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional DRAM arrays use 2-dimensional structure, then manufacturing is simpler, but memory density and capacity are limited due to sharing silicon real estate with support circuitry
Solution Approach 1:
The patent transitions from 2-dimensional DRAM arrays to 3-dimensional memory structures by stacking multiple memory layers vertically. This dimensional change allows memory cells to be arranged in three dimensions (length, width, and height), dramatically increasing memory capacity without proportionally increasing the footprint area, thereby resolving the contradiction between memory capacity and structural complexity.
Solution Approach 2:
The patent divides the memory system into multiple independent layers or stacks, where each layer contains complete memory functionality. This segmentation allows parallel operation of multiple memory layers, increasing overall capacity while distributing the complexity across modular units that can be independently manufactured and tested.
2Productivity
If conventional DRAM arrays share silicon real estate with support circuitry, then device area is reduced, but bandwidth is limited due to pin constraints and high power/latency in signal transmission
Solution Approach 1:
The patent merges the memory array and support circuitry onto the same semiconductor substrate in a unified 3-dimensional architecture. By integrating word lines, bit lines, sense amplifiers, and control logic within the same vertical stack as the memory cells, the design eliminates the need for extensive external interconnects, thereby increasing bandwidth while reducing power consumption associated with signal transmission.
Solution Approach 2:
The patent introduces local sense amplifiers and buffer circuits as intermediary elements between the memory cells and external interfaces. These intermediaries process and condition signals locally within the 3-dimensional structure, reducing the burden on external pins and decreasing the power and latency associated with long-distance signal transmission.
Data Source
AI summary
An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.