Wafer-Bonded 3D NAND Layout for High-Capacity Stable Processing
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in efficiently integrating high-capacity, fast data processing capabilities while maintaining stable real-time operations, particularly in 3D NAND flash memory systems.
Innovation Solution
A three-dimensional storage device is implemented using wafer-to-wafer bonding, comprising a first chip with a peripheral circuit region and a second chip with three-dimensional arrays of non-volatile memory cells, vertically stacked and controlled by a memory controller with integrated control logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells and word lines stacked on a substrate is increased to improve memory capacity, then the memory capacity and degree of integration are improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The storage device is divided into multiple chips (first chip with peripheral circuits, second chip with memory cell arrays) that are bonded together. This segmentation allows the memory capacity to be increased through stacking while keeping each individual chip's complexity manageable and enabling parallel processing capabilities.
Solution Approach 2:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking by bonding multiple chips together. This dimensional change enables significant increases in memory capacity and integration density without proportionally increasing the complexity of individual chip structures.
2Quantity of substance
If more memory cells are stacked to increase capacity, then the degree of integration is improved, but the stability of real-time processing deteriorates
Solution Approach 1:
By separating the device into functional segments (peripheral circuit chip and memory cell array chip), the patent enables independent optimization of each segment for its specific function, thereby maintaining processing stability while achieving high integration through stacking.
Solution Approach 2:
The bonding interface between chips acts as an intermediary that enables stable electrical and mechanical connections. This intermediary structure ensures reliable signal transmission and power delivery across the stacked architecture, maintaining real-time processing stability despite increased integration.
Data Source
AI summary
Provided is a three-dimensional storage device using wafer-to-wafer bonding. A storage device includes a first chip including a first substrate and a peripheral circuit region including a first control logic circuit configured to control operation modes of the non-volatile memory device and a second chip including a second substrate and three-dimensional arrays of non-volatile memory cells. The second chip may be vertically stacked on the first chip so that a first surface of the first substrate faces a first surface of the second substrate, and a second control logic circuit is configured to control operation conditions of the non-volatile memory device and is arranged on a second surface of the second substrate, the second surface of the second substrate being opposite to the first surface of the second substrate of the second chip.