Wafer-Bonded 3D NVM Architecture With SERDES Memory Control
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Solution Overview
Problem
Current 3D storage devices face challenges in achieving stable and efficient real-time processing of bulk data due to the increasing complexity and deterioration of nonvolatile memory (NVM) cells, which affects the reliability and performance of storage devices.
Innovation Solution
The implementation of a 3D storage device using wafer-to-wafer bonding, where a first chip with a peripheral circuit region and a second chip with 3D arrays of NVM cells are vertically stacked, and a third chip with a control circuit region, including a memory management unit (MMU) and serializer/deserializer (SERDES) interface, is used to control operation modes and conditions of the NVM cells, enhancing data processing and storage capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells and word lines stacked on substrate is increased to improve storage capacity, then storage capacity increases, but device complexity and deterioration of NVM cells increases
Solution Approach 1:
The storage device is divided into multiple chips (first chip with peripheral circuits, second chip with NVM cell arrays, third chip with control circuits) that are bonded together in a 3D stacked configuration. This segmentation allows the storage capacity to be increased by adding more chips or layers without significantly increasing the complexity of individual chip designs, as each chip can be manufactured using standardized processes.
Solution Approach 2:
The patent transitions from 2D planar storage to 3D vertical stacking by bonding multiple chips together in the thickness direction. This dimensional change enables storage capacity to scale by adding layers vertically rather than expanding horizontally, thereby increasing capacity without proportionally increasing the footprint or complexity of individual chip components.
2Quantity of substance
If more memory cells are stacked in 3D structure to increase storage capacity, then storage capacity improves, but reliability and performance stability deteriorates
Solution Approach 1:
By separating the NVM cell arrays into a dedicated second chip and bonding it to separate chips containing peripheral and control circuits, the patent isolates the high-stress memory cells from the control logic. This segmentation allows the NVM cells to be optimized for high-density stacking while the control circuits remain on separate substrates, maintaining their reliability without being affected by the deterioration issues inherent in high-density stacked cells.
3Productivity
If wafer-to-wafer bonding is used to stack chips vertically, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary bonding preparation processes where bonding surfaces are pre-formed with alignment marks and bonding pads before the actual wafer-to-wafer bonding occurs. This preliminary action allows for precise alignment and positioning to be established in advance, reducing the precision requirements during the final bonding step and enabling high integration density through vertical stacking.
Data Source
AI summary
A three-dimensional (3D) storage device using wafer-to-wafer bonding is disclosed. In the storage device, a first chip including a peripheral circuit region including a first control logic circuit configured to control operation modes of a nonvolatile memory (NVM) device is wafer-bonded with a second chip including 3D arrays of NVM cells, and a memory controller includes a third chip including a control circuit region. The control circuit region of the third chip includes a second control logic circuit associated with operation conditions of the NVM device, and the second control logic circuit includes a serializer/deserializer (SERDES) interface configured to share random access memory (RAM) in the memory controller and transmit and receive data to and from the NVM device.