Wafer-Bonded Cascode HEMT Structure for High Breakdown Voltage
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high breakdown voltages without increasing layer thicknesses, which can lead to higher manufacturing costs and defects, especially in high voltage transistor devices used in RF applications.
Innovation Solution
A cascode configuration of HEMT devices is formed by bonding wafers to create a single high-voltage transistor device, where HEMT devices are connected vertically, reducing the need for thick channel layers and minimizing conductive routing, thereby enhancing breakdown voltage and thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If layer thicknesses are increased to achieve high breakdown voltages, then breakdown voltage is improved, but manufacturing costs and defects increase
Solution Approach 1:
The patent divides the high-voltage transistor into multiple lower-voltage HEMT devices stacked vertically in a cascode configuration. Each HEMT device has a moderate breakdown voltage (e.g., 600V), but when stacked in series, they achieve the desired high breakdown voltage (e.g., 1200V) without requiring any single device to have an excessively thick channel layer, thereby avoiding the manufacturing defects and cost increases associated with thick layers.
Solution Approach 2:
The patent transitions from a planar single-device architecture to a three-dimensional stacked architecture. By stacking HEMT devices vertically along the depth dimension, the patent achieves high breakdown voltage without increasing the lateral dimensions or the channel layer thickness of individual devices, thus avoiding the manufacturing issues associated with thick layers while maintaining cost-effectiveness.
2Reliability
If layer thicknesses are increased to achieve high breakdown voltages, then breakdown voltage is improved, but device area increases
Solution Approach 1:
The patent moves the solution from the lateral plane to the vertical dimension by stacking HEMT devices. This allows high breakdown voltage to be achieved through vertical stacking rather than lateral expansion or increased layer thickness, thereby maintaining a compact device footprint and avoiding area increase.
Solution Approach 2:
The patent implements a nested structure where multiple HEMT devices are stacked one on top of another, with each device containing the necessary semiconductor layers and contacts. This nested vertical arrangement allows high breakdown voltage to be achieved within a compact volume, effectively utilizing the third dimension to reduce the required device area.
3Reliability
If wafer bonding is used to create cascode HEMT devices, then breakdown voltage and thermal performance are improved, but device complexity increases
Solution Approach 1:
The patent segments the high-voltage transistor functionality into multiple independent HEMT devices that can be manufactured separately on individual wafers using standard processes. The wafer bonding step then combines these segmented devices into a cascode structure, achieving high breakdown voltage and thermal performance while managing complexity through modular manufacturing and assembly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The cascode HEMT device achieves a breakdown voltage of 1200 V or greater with reduced device area and improved thermal behavior, efficiency, and reduced parasitic inductance, while maintaining cost-effectiveness.
Implementation Method 1
bonding wafers to create a single high-voltage transistor device
Data Source
AI summary
A semiconductor device includes a first semiconductor structure including a first high electron mobility transistor (HEMT) device, wherein the first HEMT device includes a first gate, a first source, and a first drain; and a second semiconductor structure stacked above and bonded to the first semiconductor structure, wherein the second semiconductor structure includes a second HEMT device and a third HEMT device, wherein the second HEMT device includes a second gate, a second source, and a second drain that is electrically connected to the first source, wherein the third HEMT device includes a third gate, a third source, and a third drain that is electrically connected to the first gate.