Stacked Semiconductor Package Structure for High-Density Reliability
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high integration and high speed while maintaining structural reliability, especially as they become smaller and lighter.
Innovation Solution
A semiconductor package design featuring stacked semiconductor chips with wafer-to-wafer bonding, including a first semiconductor chip and multiple second semiconductor chips, where the active surfaces of the second semiconductor substrates face the inactive surface of the first semiconductor substrate, and are electrically connected through bonding pads and insulating layers, with a package molding layer and dummy support substrates for enhanced structural support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor packages use stacked semiconductor chips to achieve high integration and high speed, then integration density and processing speed are improved, but structural reliability deteriorates due to increased complexity and bonding interface vulnerabilities
Solution Approach 1:
The patent applies beforehand cushioning by introducing a dummy support substrate beneath the stacked semiconductor chips. This dummy support substrate is positioned in advance to prevent warpage and structural failure that could occur during operation. By providing this preventive structural reinforcement before reliability issues manifest, the patent resolves the contradiction between achieving high integration through stacking and maintaining structural reliability, as the dummy support cushioning compensates for the inherent vulnerabilities introduced by multiple bonding interfaces.
2Weight of moving object
If semiconductor packages are made smaller and lighter to meet electronic apparatus demands, then compactness and weight are improved, but structural strength deteriorates
Solution Approach 1:
The patent applies composite materials by combining the semiconductor chips with a dummy support substrate and multiple bonding layers to create a hybrid structure. This composite construction allows the package to maintain small size and light weight while the dummy support substrate provides additional structural strength that compensates for the reduced dimensions. The composite structure integrates both the functional semiconductor components and the mechanical support elements, resolving the contradiction between compactness and structural strength.
3Ease of manufacture
If wafer-to-wafer bonding is used to directly stack semiconductor chips, then manufacturing complexity is reduced and productivity is improved, but bonding defect risk increases
Solution Approach 1:
The patent applies the intermediary principle by introducing a dummy support substrate as a mediator in the stacking process. This dummy support substrate serves as an intermediate layer that facilitates the wafer-to-wafer bonding process while reducing the risk of bonding defects. The intermediary structure provides a stable base for bonding operations and can help distribute stresses that might otherwise cause bonding failures, thereby resolving the contradiction between manufacturing simplicity and bonding reliability.
Data Source
AI summary
Provided is a semiconductor package including a first semiconductor chip including a first semiconductor substrate having an active surface and an inactive surface opposite to each other, a plurality of second semiconductor chips each including a second semiconductor substrate having an active surface and an inactive surface opposite to each other, and a package molding layer including a bottom molding portion on a portion of an upper surface of the first semiconductor chip, which is exposed by the lowermost second semiconductor chip, and a side molding portion on side walls of the plurality of second semiconductor chips, wherein the side molding portion of the package molding layer extends in a vertical direction from an edge of an upper surface of the bottom molding portion of the package molding layer.