Wafer-Bonded Ferroelectric Capacitors for Logic-Safe FRAM Integration
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Solution Overview
Problem
Integration of capacitors, including ferroelectric or paraelectric materials, on the same substrate as logic devices is challenging, necessitating alternate methods to couple capacitors with logic transistors for enhanced charge storage and device operation.
Innovation Solution
A method of forming stacked capacitors through wafer bonding, where a multi-layer stack is patterned on a first substrate and integrated with transistors on a second substrate, using high-temperature deposition and annealing to achieve crystallinity without thermal degradation, and incorporating encapsulation layers to protect against hydrogen diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature deposition and annealing are used to achieve crystallinity of ferroelectric materials, then the capacitor performance and charge storage capability are improved, but thermal degradation of logic transistors occurs
Solution Approach 1:
The fabrication process is divided into two separate stages: (1) forming the multi-layer stack with ferroelectric material on a first substrate at controlled temperatures, and (2) bonding the first substrate to a second substrate containing logic transistors. This segmentation allows the ferroelectric capacitor to be crystallized without exposing the transistors to high temperatures that would cause thermal degradation.
Solution Approach 2:
A wafer bonding process serves as an intermediary step between capacitor fabrication and transistor integration. The bonding interface allows thermal isolation, enabling the capacitor side to undergo high-temperature processing while the transistor side remains protected at lower temperatures, thus resolving the thermal compatibility issue.
2Productivity
If ferroelectric capacitors are integrated on the same substrate as logic devices, then device density and integration level are improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The integration architecture separates capacitor fabrication on a first substrate from transistor fabrication on a second substrate. This segmentation simplifies the manufacturing process by allowing each component to be optimized independently, reducing the overall process complexity while achieving high device density through subsequent wafer bonding.
Solution Approach 2:
Instead of integrating capacitors and transistors in the same planar layer, the invention moves to a three-dimensional stacked architecture where capacitors are formed on one wafer and transistors on another, then bonded together. This dimensional transition reduces in-plane complexity while increasing vertical integration density.
3Reliability
If encapsulation layers are added to protect against hydrogen diffusion, then capacitor reliability is improved, but manufacturing steps and process time increase
Solution Approach 1:
Encapsulation layers are deposited on the multi-layer stack before wafer bonding, in advance of the final device assembly. This preliminary encapsulation protects the ferroelectric material from hydrogen diffusion during subsequent processing and operation, ensuring long-term reliability without requiring additional post-bonding steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the integration of high-density ferroelectric RAM devices with reduced thermal impact on transistors, enhancing device performance and environmental sustainability by using lead-free perovskite materials.
Implementation Method 1
bonding a first conductive layer formed above a transistor of a first substrate with a second conductive layer formed above a multi-layer stack of a second substrate
Implementation Method 2
using high-temperature deposition and annealing to achieve crystallinity without thermal degradation
Implementation Method 3
incorporating encapsulation layers to protect against hydrogen diffusion
Data Source
AI summary
A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.