Wafer Bonded GaN Monolithic Integrated Circuits
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Solution Overview
Problem
The challenge lies in integrating dissimilar semiconductor materials with significantly different lattice constants to form monolithic semiconductor devices, as conventional epitaxial growth techniques are limited by lattice matching constraints, making it difficult to create robust heterojunctions for advanced electronic and photonic circuits.
Innovation Solution
The use of wafer bonding technology allows for the monolithic integration of semiconductor materials with different lattice constants by forming a heterointerface without the need for lattice matching, using techniques such as covalent, hydrophilic, or van der Waals bonding, enabling the creation of composite structures for devices like HEMTs, lasers, and solar cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional epitaxial growth techniques are used, then lattice matching is maintained, but integration of dissimilar semiconductor materials with different lattice constants is limited
Solution Approach 1:
The patent employs a buffer layer as an intermediary between dissimilar semiconductor materials with different lattice constants. This buffer layer mediates the lattice mismatch, enabling successful epitaxial growth of high-electron-mobility transistors on substrates with significantly different lattice parameters while maintaining device performance
Solution Approach 2:
The patent modifies growth parameters including temperature, pressure, and composition gradients during epitaxial growth to accommodate lattice mismatch. By dynamically adjusting these parameters, the process enables integration of dissimilar materials while controlling defect formation and maintaining crystalline quality
2Adaptability or versatility
If wafer bonding is used to integrate dissimilar materials, then lattice matching constraints are overcome, but process complexity increases
Solution Approach 1:
The patent divides the integration process into separate stages: fabricating HEMT devices on one wafer, fabricating photonic devices on another wafer, and then bonding the wafers together. This segmentation allows each device type to be optimized independently while simplifying the overall manufacturing process
Solution Approach 2:
The patent uses a bonding interface layer as an intermediary between the HEMT wafer and photonic wafer. This intermediary layer facilitates reliable wafer bonding while accommodating thermal expansion differences and stress mismatches between dissimilar materials
3Reliability
If monolithic integration is achieved, then device performance and radiation hardness are improved, but manufacturing time and cost increase
Solution Approach 1:
The patent merges HEMT fabrication and photonic device fabrication into a single monolithic integration process using wafer bonding. This combining approach achieves radiation-hardened performance while improving manufacturing efficiency by eliminating separate assembly steps and reducing the number of handling operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates the development of high-performance, radiation-hardened semiconductor devices suitable for military and space applications, offering faster processing times, reduced equipment costs, and the ability to integrate diverse semiconductor materials into a single composite structure, overcoming the limitations of traditional epitaxial growth methods.
Implementation Method 1
forming a heterointerface without the need for lattice matching, using techniques such as covalent, hydrophilic, or van der Waals bonding
Implementation Method 2
forming a heterointerface without the need for lattice matching, using techniques such as covalent, hydrophilic, or van der Waals bonding
Implementation Method 3
forming a heterointerface without the need for lattice matching, using techniques such as covalent, hydrophilic, or van der Waals bonding
Data Source
AI summary
Wafer bonded GaN monolithic integrated circuits and methods of manufacture of wafer bonded GaN monolithic integrated circuits and their related structures for electronic and photonic integrated circuits and for multi-functional integrated circuits, are described herein. Other embodiments are also disclosed herein.