Wafer-Bonded Gate Stack Structure for High-Density Memory Integration
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Solution Overview
Problem
Semiconductor devices face challenges in maintaining high-capacity data processing while reducing device volume, necessitating improved integration and reliability.
Innovation Solution
A semiconductor device design incorporating a substrate with peripheral circuits, junction pads, insulating structures, passivation layers, and conductive patterns, featuring a stack structure with gate layers and a vertical structure for data storage, utilizing distinct materials in the barrier capping layer and upper insulating structure to enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If structures are joined using a wafer bonding method to improve integration, then the degree of integration is improved, but the device volume reduction goal may be compromised due to bonding process complexity
Solution Approach 1:
The device is divided into two separate structures (first structure with peripheral circuit and second structure with gate layers) that are joined through wafer bonding. This segmentation allows each structure to be optimized independently while achieving high integration through the bonding process, resolving the contradiction between integration complexity and volume reduction.
Solution Approach 2:
The first structure and second structure are joined in a nested configuration where the gate layers of the second structure are positioned over the channel layers of the first structure. This nesting approach maximizes space utilization and achieves high integration without proportionally increasing the overall device volume.
2Reliability
If multiple insulating structures and barrier capping layers are added to enhance reliability, then the reliability is improved, but the device complexity increases
Solution Approach 1:
Different insulating structures (first insulating structure, second insulating structure, upper insulating structure) and barrier capping layers are strategically positioned at specific locations where reliability enhancement is most needed. This local quality approach improves reliability without uniformly increasing the complexity of the entire device structure.
Solution Approach 2:
The device employs composite material structures including multiple insulating materials and barrier capping layers with different material properties. These composite structures provide enhanced reliability through material synergy while maintaining a manageable level of device complexity through systematic material selection and arrangement.
Data Source
AI summary
A device including a first structure and a second structure is provided. The device includes a substrate, a peripheral circuit and first junction pads on the substrate; a first insulating structure surrounding side surfaces of the first junction pads; second junction pads contacting the first junction pads; a second insulating structure on the first insulating structure; a passivation layer on the second insulating structure; an upper insulating structure between the passivation layer and the second insulating structure; a barrier capping layer between the upper insulating structure and the passivation layer; conductive patterns spaced apart from each other in the upper insulating structure; a first pattern structure between the upper insulating structure and the second insulating structure; a stack structure between the second insulating structure and the first pattern structure, and including gate layers; and a vertical structure passing through the stack structure and including a data storage structure and a channel layer.