Wafer-to-Wafer Bonded Memory Dies for Warpage Control
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Solution Overview
Problem
The challenge is to achieve thinner semiconductor dies for high-capacity storage devices without encountering mechanical issues such as warping, cracking, and chipping, which are exacerbated by thermal expansion mismatches between memory device layers and silicon substrates.
Innovation Solution
The solution involves forming a pair of semiconductor dies with their active surfaces facing each other, allowing their disparate thermal expansion coefficients to balance and prevent warping, while being physically and electrically coupled using wafer-to-wafer bonding techniques, allowing for thinner die thicknesses without mechanical failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor die thickness is reduced to increase storage capacity, then storage density is improved, but mechanical reliability deteriorates due to warping, cracking, and chipping
Solution Approach 1:
The invention divides a single thick die into multiple thinner dies stacked together. Each thin die has reduced individual thickness (e.g., 15-25 microns) which eliminates warping and cracking issues, while the stack achieves the required total storage capacity. The segmentation allows each layer to be mechanically reliable while collectively providing high density.
Solution Approach 2:
Multiple thin semiconductor dies are stacked and nested vertically one on top of another, with each die containing memory cells formed in successive layers. This nesting approach achieves high storage capacity within a compact volume while maintaining mechanical integrity of individual thin layers.
2Quantity of substance
If semiconductor die thickness is reduced below 36 microns, then storage density is improved, but mechanical stability worsens due to thermal expansion mismatch causing warping
Solution Approach 1:
The thick die is segmented into multiple thin dies (e.g., two 18-micron dies instead of one 36-micron die). Each thin die has sufficient mechanical stability because the reduced thickness minimizes thermal stress accumulation, preventing warping while achieving the required storage density when stacked.
Solution Approach 2:
The invention uses composite structures with different materials (memory device layers on silicon substrate) where each material layer is kept thin. The composite stacking approach allows thermal expansion mismatches to be managed across multiple thin interfaces rather than creating excessive stress in a single thick structure.
3Quantity of substance
If semiconductor die thickness is reduced, then storage capacity is improved, but manufacturing complexity increases due to handling and assembly difficulties
Solution Approach 1:
The manufacturing process segments the creation of thin dies that can be handled more easily than a single thick die. Each thin die can be processed, tested, and assembled independently, reducing the complexity of handling extremely thin materials while achieving high storage capacity through stacking.
Solution Approach 2:
Multiple thin dies are prepared and pre-assembled in a controlled manufacturing process before final packaging. This preliminary assembly of thin layers while they are still manageable simplifies the overall manufacturing complexity compared to attempting to handle and process a single ultra-thin die.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables semiconductor dies to be made thinner than previously feasible, reducing warpage and preventing chipping or cracking, thereby increasing storage capacity in the same form factor and doubling memory density while maintaining reliability.
Implementation Method 1
heating of the semiconductor dies during package fabrication causes the dies to warp given the different coefficients of thermal expansion between the memory device layers and silicon substrate
Implementation Method 2
physically and electrically coupled using wafer-to-wafer bonding techniques
Data Source
AI summary
A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. Once bonded, respective inactive surfaces of the wafers may be thinned and then the die pairs diced from the wafers to form a completed memory module. When the wafers are bonded face to face, they compensate each other, mechanically resulting in the die pair having a minimum warpage.