Wafer-Bonded Memory Layout to Prevent Bonding Pad Overlap
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Solution Overview
Problem
Existing memory devices face challenges in efficiently connecting and integrating peripheral circuits with memory cell arrays, leading to complex wiring structures and potential bridge failures due to overlapping bonding pads.
Innovation Solution
A memory device with a wafer-to-wafer bonding structure, where peripheral circuits associated with bit lines and word lines are separated onto different wafers, reducing the need for overlapping bonding pads and simplifying the connection structure, allowing for increased space for peripheral circuits and improved connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If peripheral circuits are integrated on the same wafer as the memory cell array, then device functionality is complete, but wiring complexity increases and bridge failures occur due to overlapping bonding pads
Solution Approach 1:
The memory device is divided into three separate wafers: a first wafer containing peripheral circuits (page buffer circuit and data input/output circuit), a second wafer containing the memory cell array, and a third wafer containing control circuits (row decoder and voltage generator). This segmentation separates bonding pads onto different wafers, eliminating overlaps and reducing bridge failure risks while simplifying the wiring structure.
2Productivity
If bonding pads are placed on the same wafer surface, then connection density is high, but overlapping pads cause manufacturing defects
Solution Approach 1:
The solution transitions from a two-dimensional layout where all bonding pads must coexist on the same wafer surface to a three-dimensional stacked wafer structure. By distributing bonding pads across different wafer surfaces (first wafer bottom surface, second wafer top and bottom surfaces, third wafer top surface), the patent eliminates spatial conflicts and alignment precision requirements while maintaining high connection density through vertical integration.
3Area of stationary object
If wafer bonding structure is implemented with multiple wafers, then peripheral circuit space is increased, but manufacturing process complexity increases
Solution Approach 1:
Peripheral circuits are formed on the first wafer before bonding to the second wafer, and control circuits are formed on the third wafer before bonding to the second wafer. This preliminary formation of circuits on separate wafers allows for optimized circuit layout and manufacturing on each individual wafer, reducing overall process complexity compared to forming all circuits on a single large wafer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure enhances high-speed operation and reduces power consumption by minimizing wiring length and bridge failures, enabling increased capacity and performance through multi-plane and multi-bank configurations.
Implementation Method 1
a second wafer having a first surface bonded to the first wafer and a second surface opposite to the first surface in a first direction
Data Source
AI summary
A memory device includes a first wafer including a page buffer circuit and a data input/output circuit connected to the page buffer circuit; a second wafer having a first surface bonded to the first wafer and a second surface opposite to the first surface in a first direction and including a plurality of word lines, a memory cell array, and a plurality of bit lines connected to the page buffer circuit; and a third wafer bonded to the second surface of the second wafer and including a row decoder connected to the plurality of word lines and a voltage generator that provides an operating voltage to the row decoder.