Wafer-Bonded MIM Capacitor Structure Without Insulating Film Damage
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Solution Overview
Problem
The formation of MIM capacitive elements is prone to process damage during the formation of electrodes and contacts, which degrades the capacitive insulating film, posing a challenge in reducing chip size due to the large mounting area required by capacitive elements.
Innovation Solution
A semiconductor device and manufacturing method involving wafer bonding of multilayer wiring layers from two semiconductor substrates to form MIM capacitive elements without process damage, where one electrode is formed with a conductive layer from each substrate, and a capacitive insulating film is interposed between the electrodes, allowing for a smaller footprint and avoiding damage to the insulating film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MIM capacitive element formation process is used, then capacitive elements can be formed, but process damage occurs to the capacitive insulating film during electrode and contact formation
Solution Approach 1:
The manufacturing process is divided into two separate stages: (1) forming the capacitive insulating film and lower electrode on the first substrate, then (2) forming the upper electrode on the second substrate and bonding the substrates together. This segmentation allows the capacitive insulating film to be formed before any processes that could cause damage, and the upper electrode to be formed separately on a different substrate, thereby eliminating process damage to the insulating film.
Solution Approach 2:
The capacitive insulating film is formed in advance on the first substrate before any electrode formation processes that could cause damage. The lower electrode is also formed beforehand. This preliminary action ensures that the insulating film is already in place and protected when subsequent electrode formation processes occur on separate substrates.
2Quantity of substance
If capacitive elements are formed using conventional methods, then they provide necessary capacitance, but they require large mounting area which conflicts with transistor size reduction trend
Solution Approach 1:
The invention transitions from planar capacitive element formation to three-dimensional stacked configuration by bonding two substrates together. The capacitive element utilizes the vertical dimension between the two bonded substrates, with the capacitive insulating film positioned in the inter-substrate space. This dimensional change allows high capacitance to be achieved without increasing the planar mounting area, as the capacitance is generated in the vertical direction between electrodes on different substrates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of MIM capacitive elements without process damage, reducing the mounting area and maintaining the integrity of the capacitive insulating film, thus aligning with the trend of transistor size reduction and minimizing chip size.
Implementation Method 1
wiring layers of the first multilayer wiring layer and the second multilayer wiring layer being bonded to each other by wafer bonding
Data Source
AI summary
The present technology relates to a semiconductor device in which a MIM capacitive element can be formed without any process damage, and a method for manufacturing the semiconductor device. In a semiconductor device, wiring layers of a first multilayer wiring layer formed on a first semiconductor substrate and a second multilayer wiring layer formed on a second semiconductor substrate are bonded to each other by wafer bonding. The semiconductor device includes a capacitive element including an upper electrode, a lower electrode, and a capacitive insulating film between the upper electrode and the lower electrode. One electrode of the upper electrode and the lower electrode is formed with a first conductive layer of the first multilayer wiring layer and a second conductive layer of the second multilayer wiring layer. The present technology can be applied to a semiconductor device or the like formed by joining two semiconductor substrates, for example.