Wafer-Bonded Modular Memory Units for Concurrent High-Bandwidth Access
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Solution Overview
Problem
Conventional dynamic random-access memory (DRAM) arrays are limited by their 2-dimensional structure, leading to lower density and capacity compared to 3-D NOR memory arrays, and face challenges with high power consumption and latency due to pin limitations in communication between wire-bonded circuits.
Innovation Solution
The integration of a memory circuit with a 3-D NOR memory array and a logic circuit using wafer bonding techniques, such as flip-chip or TSV, to create a high-bandwidth, high-capacity memory system with low-latency and low-power connections, enabling modular and segmented memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2-dimensional DRAM arrays are used, then manufacturing is simpler, but memory density and capacity are limited
Solution Approach 1:
The patent transitions from conventional 2-dimensional DRAM arrays to 3-dimensional NOR memory arrays, stacking memory cells vertically to achieve higher density and capacity while maintaining manufacturability through advanced fabrication processes
2Use of energy by moving object
If wire-bonded circuits are used for communication, then device complexity is reduced, but power consumption increases and latency increases due to pin limitations
Solution Approach 1:
The patent merges the memory circuit and logic circuit onto a single semiconductor substrate, eliminating the need for wire-bonded interconnections and reducing power consumption and latency by providing direct integrated communication pathways
3Speed
If conventional DRAM architecture is used, then ease of operation is maintained, but access speed and bandwidth are limited
Solution Approach 1:
The patent segments the memory array into multiple independently accessible blocks with dedicated control circuits, enabling parallel access operations and increasing bandwidth while maintaining ease of operation through standardized memory interfaces
Data Source
AI summary
An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.