Wafer-Bonded Package Architecture for Thin III-V Die Handling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
III-V devices, such as gallium arsenide and gallium nitride, are challenging to process and package due to mechanical handling damages, requiring enhanced mechanical robustness without compromising operating frequency or thermal performance.
Innovation Solution
A package architecture with a wafer-to-wafer bonding process that includes a package carrier with mounted device dies, a heat spreader, and a die carrier, utilizing materials like silicon, silicon carbide, and III-V materials, along with a thermal interface layer and underfilling material to provide mechanical robustness and thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If III-V devices are thinned to reduce passive circuit size, then operating frequency is improved, but mechanical robustness deteriorates making the devices difficult to process and package
Solution Approach 1:
The patent embeds the thinned III-V device body within a die carrier structure, creating a nested configuration where the fragile device is protected by the surrounding carrier. This allows the device to maintain its thinned profile for high-frequency operation while gaining mechanical strength from the carrier enclosure.
Solution Approach 2:
The patent creates a composite structure combining the III-V device body with the die carrier material (such as silicon, silicon carbide, or other substrates). This composite construction provides the mechanical robustness of the carrier material while preserving the electrical and frequency characteristics of the III-V device.
2Strength
If wafer to wafer bonding is used to enhance mechanical robustness, then handling damage is reduced, but processing complexity increases
Solution Approach 1:
The patent merges the III-V device wafer with a carrier wafer through wafer-to-wafer bonding, combining two separate wafers into a single integrated structure. This merging provides mechanical robustness while the bonding process itself becomes a standardized step in the manufacturing flow.
Solution Approach 2:
The wafer bonding is performed as a preliminary action before subsequent packaging and processing steps. By establishing the mechanically robust bonded structure early in the manufacturing process, the patent enables easier handling and processing in later stages without requiring complex protective measures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the mechanical robustness and thermal performance of III-V devices during packaging, preventing damage and maintaining high-frequency operation, while allowing for the thinning of III-V devices to reduce passive circuit size without sacrificing performance.
Implementation Method 1
A package architecture with a wafer-to-wafer bonding process that includes a package carrier with mounted device dies
Implementation Method 2
a heat spreader... along with a thermal interface layer... to provide mechanical robustness and thermal performance
Data Source
AI summary
The present disclosure relates to a package architecture and a method for making the same. The disclosed package architecture includes a package carrier, a first device die and a second device die mounted on the package carrier, and a heat spreader. The first device die includes a first device body with a thickness between 5 μm and 130 μm, a die carrier, and an attachment section between the first device body and the die carrier, while the second device die includes a second device body. The first device body and the second device body are formed of different materials. A top surface of the die carrier of the first device die and a top surface of the second device body of the second device die are substantially coplanar. The heat spreader resides over the top surface of the die carrier and the top surface of the second device body.