Direct Wafer-Bonded SiC-Si Layers for Low-Defect Power MOSFETs
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Solution Overview
Problem
Semiconductor devices, particularly power MOSFETs, face challenges in forming three-dimensional structures with high aspect ratios, leading to defects like triangle defects, carrot defects, and lattice mismatches between dissimilar materials such as Si and SiC, which increase manufacturing costs and reduce yield, especially in harsh radiation environments.
Innovation Solution
A method of forming a sacrificial heteroepitaxy interface with inverted pyramids and micropillars to confine defects to sacrificial layers, followed by removal, using direct wafer bonding (DWB) to create a substantially defect-free SiC substrate, and integrating this with MEMS and WBG materials to form high-breakdown voltage trench gate power MOSFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If SiC layer is formed on Si substrate, then high breakdown voltage and high power density are achieved, but heterointerface defects increase due to lattice mismatch and CTE difference
Solution Approach 1:
The patent segments the SiC layer into multiple thin epitaxial layers grown on patterned Si substrate with inverted pyramids and micropillars. This segmentation reduces the continuous heterointerface area, confining defects to specific regions while maintaining overall high breakdown voltage performance.
Solution Approach 2:
The patent extracts and removes the defective heterointerface regions through selective etching of the Si substrate beneath inverted pyramids and micropillars. This extraction eliminates triangle defects, carrot defects, and other interface-related defects while preserving the functional SiC device structures.
2Power
If three-dimensional device structures with high aspect ratio are formed, then power density is increased, but manufacturing complexity and defect density increase
Solution Approach 1:
The patent performs preliminary patterning of the Si substrate with inverted pyramids and micropillars before growing the SiC epitaxial layers. This preliminary action prepares the substrate to guide subsequent SiC layer formation, enabling high aspect ratio structures to be formed more easily with reduced defect propagation.
Solution Approach 2:
The patent applies local quality by creating regions of different Si substrate morphology (inverted pyramids vs. flat areas vs. micropillars) to control where defects form and where high-quality SiC structures are grown. This local differentiation allows high power density structures in specific regions while managing overall manufacturing complexity.
3Manufacturing precision
If multiple mask layers are used in multi-epi manufacturing, then defect control is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent inverts the conventional approach by first creating the Si substrate pattern (inverted pyramids and micropillars) and then growing SiC layers conformally on this pattern. This inversion reduces the need for multiple mask layers during SiC growth, as the substrate pattern itself guides the epitaxial layer formation and defect confinement.
Solution Approach 2:
The Si substrate pattern with inverted pyramids and micropillars serves multiple functions: it guides epitaxial growth, confines defects to specific regions, and enables subsequent selective removal. This multi-functionality reduces the need for separate process steps and mask layers, lowering manufacturing cost while maintaining defect control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in a cost-effective, defect-free SiC substrate suitable for harsh radiation environments, enhancing reliability and performance of power MOSFETs by reducing defects and improving breakdown voltage.
Implementation Method 1
forming the SiC layer on a Si layer produces a heterointerface
Implementation Method 2
method of direct wafer bonding between semiconductor layers
Data Source
AI summary
A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The first semiconductor material is substantially defect-free silicon carbide, and the second semiconductor material is silicon. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET, diode, insulated gate bipolar transistor, cluster trench insulated gate bipolar transistor, and thyristor. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.