Wafer Bonding via Adhesive Layer for Through Silicon Vias

Solution Overview

Problem

The existing methods for forming through silicon vias in stacked integrated circuit devices are complex and costly due to the requirement of forming bump pads, which involve seeding, electroplating, photolithography, and etching processes.

Innovation Solution

Bonding wafers before the formation of through silicon vias without positioning a bump pad between the stacking and bottom wafers, using an intervening adhesive layer and forming conductive vias that penetrate through the stacking wafer into the bottom wafer in a substantially linear manner.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bump pads are formed between stacking wafers and bottom wafers using existing methods, then electrical connection between wafers is achieved, but processing complexity and manufacturing cost increase significantly

Engineering Contradiction:

Improveelectrical connectionVSAvoidprocessing complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by bonding the stacking wafer to the bottom wafer BEFORE forming the through silicon via. This reverses the conventional sequence where bump pads are formed first. By bonding wafers in advance using an adhesive layer, the need for complex bump pad formation processes (seeding, electroplating, photolithography, etching) is eliminated, while electrical connection is still achieved through the via formed later.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If bump pads are formed between stacking wafers and bottom wafers, then electrical connection is established, but manufacturing cost increases due to multiple processing steps

Engineering Contradiction:

Improveelectrical connectionVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by bonding the stacking wafer to the bottom wafer BEFORE forming the through silicon via. This reverses the conventional sequence where bump pads are formed first. By bonding wafers in advance using an adhesive layer, the need for complex bump pad formation processes (seeding, electroplating, photolithography, etching) is eliminated, while electrical connection is still achieved through the via formed later.

Inventive Principle:

Principle #10Preliminary action

3Device complexity

If wafers are bonded before through silicon via formation, then processing complexity and cost are reduced, but via alignment precision must be maintained

Engineering Contradiction:

Improveprocessing complexityVSAvoidvia alignment precision

Core Design Contradiction:

Device complexityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by bonding the stacking wafer to the bottom wafer BEFORE forming the through silicon via. This reverses the conventional sequence where bump pads are formed first. By bonding wafers in advance using an adhesive layer, the need for complex bump pad formation processes (seeding, electroplating, photolithography, etching) is eliminated, while electrical connection is still achieved through the via formed later.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the processing and reduces costs by eliminating the need for bump pad formation between wafers, thereby addressing the complexity and expense issues in existing techniques.

Implementation Method 1

bonding wafers before the formation of the through silicon via by bonding wafers before the formation of the through silicon via such that no bump pad is positioned between the stacking wafer and the bottom wafer

Methodology Applied

Scientific EffectAdhesive bonding: Adhesive

Data Source

PatentUS8421193B2Integrated circuit device having through via and method for preparing the same

Publication Date: 2013.04.16 NAN YA TECH

AI summary

An integrated circuit device includes a bottom wafer, at least one stacking wafer positioned on the bottom wafer, and at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein the bottom wafer and the stacking wafer are bonded by an intervening adhesive layer, and no bump pad is positioned between the bottom wafer and the stacking wafer. A method for preparing an integrated circuit device includes the steps of forming a bottom wafer, forming at least one stacking wafer, bonding the at least one stacking wafer to the bottom wafer by an intervening adhesive layer, and forming at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein no bump pad is positioned between the bottom wafer and the stacking wafer.