Wafer Bonding Alignment Compensation via Run-Out Misalignment Measurement
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Solution Overview
Problem
The challenge in semiconductor technology is achieving accurate bonding alignment with submicron precision, essential for higher device integration and miniaturization, as existing techniques fail to compensate for misalignments effectively in wafer bonding processes.
Innovation Solution
A method and system for wafer bonding alignment compensation, which involves measuring alignment positions of bonding alignment marks, calculating mean run-out misalignment, and using a wafer deformation adjustment module to compensate for misalignments during bonding, ensuring translational, rotational, and run-out misalignments are within allowable error ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional wafer bonding alignment techniques are used, then the bonding process can be completed, but the alignment precision cannot achieve submicron level due to uncorrected run-out misalignment
Solution Approach 1:
The system performs preliminary measurement of run-out misalignment using alignment marks before the actual bonding process. The measured data is used to pre-calculate compensation values that are applied during bonding, allowing the system to correct alignment errors before they affect the final bonding precision
Solution Approach 2:
The system establishes a feedback loop where alignment marks are measured to detect run-out misalignment, the data is processed to determine compensation values, and these values are fed back to adjust the wafer positioning system. This closed-loop control enables continuous improvement of alignment precision beyond what conventional open-loop systems can achieve
2Manufacturing precision
If wafer deformation adjustment is implemented to compensate for run-out misalignment, then alignment accuracy is improved, but the device complexity increases
Solution Approach 1:
The system changes the operational parameters of the wafer handling system by dynamically adjusting positioning and deformation parameters based on measured run-out misalignment. This allows the same hardware to achieve higher precision without adding fundamentally new components, thereby limiting the increase in device complexity
Data Source
AI summary
Embodiments of methods and systems for wafer bonding alignment compensation are disclosed. The method comprises bonding a first pair of wafers including a first wafer and a second wafer, wherein the first pair of wafers have a plurality of corresponding bonding alignment mark pairs each including a first bonding alignment mark on the first wafer and a second bonding alignment mark on the second wafer; measuring alignment positions of the plurality of bonding alignment mark pairs; determining a mean run-out misalignment between the first pair of wafers using the alignment measurement, wherein the mean run-out misalignment indicates a deformation of at least one of the first pair of wafers; and during bonding of a second pair of wafers, controlling a wafer deformation adjustment module to compensate for the run-out misalignment based on the mean run-out misalignment of the first pair of wafers.