Wafer Bonding Dummy Pad Layout to Prevent Dicing Cracks
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Solution Overview
Problem
Wafer-to-wafer bonding in semiconductor devices often results in delamination and cracks due to external forces applied during the dicing process, which compromises the junction force between upper and lower chips.
Innovation Solution
Incorporating dummy patterns on the bonding surfaces of wafers within the scribe lane area, which are exposed on the edges of the chips and bonded together during laser processing, enhancing the junction force and preventing defects like delamination and cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If wafer-to-wafer bonding is performed without dummy patterns, then the manufacturing process is simpler, but the junction force between chips is insufficient causing delamination and cracks
Solution Approach 1:
The bonding surface is segmented into functional regions (bonding pads) and dummy pattern regions. The dummy patterns are separate structural elements positioned at specific locations (edges, corners, or distributed) to provide mechanical reinforcement without interfering with the electrical bonding function of the bonding pads.
Solution Approach 2:
Dummy patterns are formed on the wafer surfaces before the bonding process. These pre-formed structures prepare the bonding interface to withstand subsequent mechanical stresses during dicing and packaging, preventing delamination and cracks that would occur without such preliminary reinforcement.
2Reliability
If dummy patterns are added to increase bonding strength, then delamination and cracks are prevented, but the manufacturing complexity increases
Solution Approach 1:
The formation of dummy patterns is merged with existing manufacturing processes such as photolithography and etching steps already used for creating bonding pads and circuit patterns. This integration allows dummy patterns to be formed simultaneously with other structures, minimizing additional process complexity.
3Manufacturing precision
If dummy patterns are positioned in the scribe lane area, then laser processing can remove excess material to prevent defects, but the processing time increases
Solution Approach 1:
Laser processing selectively removes material only in the scribe lane areas where dummy patterns extend, skipping the chip areas. This targeted approach quickly eliminates excess material and prevents dicing defects without requiring prolonged processing time across the entire wafer surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dummy patterns increase the bonding strength between chips, effectively preventing delamination and cracks, thereby improving the integrity of semiconductor devices manufactured through wafer-to-wafer bonding.
Implementation Method 1
Wafer-to-wafer bonding is a technology of compressing the upper wafer and the lower wafer and then annealing them to directly bond them without a separate connection structure such as a solder bump
Implementation Method 2
laser processing the first wafer and the second wafer along between a scribe lane area, wherein at least a part of each of the first dummy pattern and the second dummy pattern is positioned in the scribe lane area to be processed by the laser processing
Data Source
AI summary
Some embodiments of the present disclosure relate to a semiconductor device including a first semiconductor chip comprising a first bonding pad and one or more first dummy pads; and a second semiconductor chip, positioned on the first semiconductor chip, comprising a second bonding pad and one or more second dummy patterns; wherein the first bonding pad is in contact with the second bonding pad, the first dummy pattern is in contact with the second dummy pattern, the first dummy pattern is positioned at an edge of the first semiconductor chip configured to be exposed from a side surface of the first semiconductor chip, and the second dummy pattern is positioned at an edge of the second semiconductor chip configured to be exposed to a side surface of the second semiconductor chip.