Wafer Bonding Structure With Dangling-Bond Pads to Prevent Edge Voids

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Solution Overview

Problem

Existing semiconductor structures face challenges in increasing bonding strength during wafer bonding processes to prevent edge bonding voids.

Innovation Solution

A semiconductor structure is designed with a silicon-rich oxide layer as dangling-bond pads, a nitrogen-doped silicon carbide bonding dielectric layer, and a silicon oxide top dielectric layer, along with copper pads, to enhance bonding strength and prevent void formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If direct wafer bonding is performed without additional bonding structures, then the process is simple, but bonding strength is insufficient and edge bonding voids occur

Engineering Contradiction:
Improvebonding strengthVSAvoidstructure complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The bonding interface is segmented into multiple functional components: copper pads for electrical bonding, dangling-bond pads for mechanical bonding, and dielectric layers for structural support. This segmentation allows each component to contribute specifically to bonding strength while maintaining overall structural integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bonding structure uses composite materials including silicon-rich oxide for dangling-bond pads, nitrogen-doped silicon carbide for the bonding dielectric layer, and silicon oxide for the top dielectric layer. These composite materials provide enhanced bonding strength and void prevention compared to single-material approaches.

Inventive Principle:
Principle #40Composite materials

2Reliability

If bonding strength is increased by adding more bonding interfaces, then edge bonding voids are reduced, but the manufacturing process becomes more complex

Engineering Contradiction:
Improvebonding reliabilityVSAvoidmanufacturing ease
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The copper pads and dangling-bond pads are formed in advance within the dielectric layers before the final bonding process. This preliminary formation of bonding structures ensures proper alignment and reduces manufacturing complexity during the actual bonding operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent specifies precise parameter ranges for dielectric layer thicknesses (top dielectric layer: 9000-9500 angstroms, bonding dielectric layer: 1500-2100 angstroms) and pad configurations to optimize bonding reliability while maintaining manufacturability through standardized dimensional controls.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If multiple dielectric layers and pads are added to prevent edge voids, then bonding quality improves, but device complexity increases

Engineering Contradiction:
Improvebonding precisionVSAvoidlayer structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Different regions of the bonding structure have specialized properties: copper pads provide electrical conductivity and bonding strength, dangling-bond pads provide mechanical interlocking, and dielectric layers provide structural support and insulation. This local differentiation optimizes bonding precision without requiring uniform complexity throughout the entire structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The bonding structure extends into the vertical dimension with multiple stacked dielectric layers and embedded pads at different depths. This three-dimensional arrangement improves bonding precision by distributing bonding forces across multiple interfaces rather than relying on a single planar bonding surface.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250210553A1Semiconductor structure and fabrication method thereof
Publication Date: 2025.06.26 UNITED MICROELECTRONICS CORP
  • US20250210553A1 patent drawing
  • US20250210553A1 patent drawing
  • US20250210553A1 patent drawing

AI summary

A semiconductor structure includes a semiconductor substrate; an interconnection structure disposed on the semiconductor substrate; a cap layer disposed on the interconnection structure; a top dielectric layer disposed on the cap layer; a bonding dielectric layer disposed on the top dielectric layer; a plurality of copper pads disposed in the bonding dielectric layer, the top dielectric layer and the cap layer; and a plurality of dangling-bond pads disposed in the bonding dielectric layer and the top dielectric layer.