Wafer Bonding Structure With Filling Layers for Void-Free Contact
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Solution Overview
Problem
The semiconductor industry faces challenges in substrate bonding during the manufacturing process of semiconductor devices, particularly in achieving strong and reliable bonding between device substrates and carrier substrates, which affects the efficiency and yield of semiconductor production.
Innovation Solution
A method involving the formation of a first filling layer on the peripheral region of the device substrate, a second filling layer with a different polishing rate, and a polishing stop layer to create a planarized surface, followed by bonding the device substrate to a carrier substrate through these layers, enhancing the bonding area and contact surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If substrate bonding is performed without filling layers, then the manufacturing process is simpler, but the bonding strength and reliability are insufficient due to non-bonding areas and voids
Solution Approach 1:
The patent applies preliminary action by forming filling layers (first filling layer 41 and second filling layer 42) on the substrate surfaces before the bonding process. These filling layers pre-fill the peripheral regions and voids that would otherwise remain empty during bonding, ensuring complete contact surfaces and eliminating non-bonding areas before the actual bonding occurs. This preliminary preparation of the bonding interface directly improves bonding strength and reliability.
2Reliability
If the contact surface between substrates is increased by adding filling layers, then bonding strength improves, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies local quality by creating filling layers with specific properties in specific locations - the first filling layer 41 is formed on the peripheral region of the substrate, and the second filling layer 42 is formed in the corner region. Each filling layer has a different polishing rate (the second filling layer has a lower polishing rate than the first), allowing selective removal to expose different surfaces. This localized approach increases the contact surface area for bonding while maintaining ease of manufacture through targeted material deposition and removal.
3Reliability
If filling layers are formed to eliminate non-bonding areas, then bonding reliability improves, but the manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the filling structure into multiple distinct layers: a first filling layer 41 and a second filling layer 42, each with different properties and functions. The first filling layer addresses the peripheral region, while the second filling layer addresses the corner region. This segmented approach allows each layer to be optimized for its specific function and enables selective polishing to expose the appropriate surfaces for bonding, improving bonding reliability without requiring a single complex filling structure.
Data Source
AI summary
A method for manufacturing a semiconductor structure includes: forming a semiconductor device on a main region of the device substrate, the device substrate having a peripheral region surrounding the main region; forming a first filling layer on the peripheral region of the device substrate; forming a second filling layer over the first filling layer and the semiconductor device after forming the first filling layer, the second filling layer having a polishing rate different from that of the first filling layer; performing a planarization process over the second filling layer to remove a portion of the second filling layer so that a remaining portion of the second filling layer has a planarized surface opposite to the device substrate; and bonding the device substrate to a carrier substrate through the first filling layer and the remaining portion of the second filling layer.