Wafer Bonding Layout for Flatness and Alignment Precision

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Solution Overview

Problem

Current methods for bonding wafers carrying semiconductor devices, such as CMOS image sensors, face issues with uneven flatness and misalignment due to chemical mechanical polishing processes.

Innovation Solution

A method involving providing a device wafer and a blanket wafer, forming a doped region on the blanket wafer, bonding them with an anneal process to separate the wafers, and planarizing the bonded wafer, followed by forming conductive patterns and metal interconnections to improve flatness and alignment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of substance

If chemical mechanical polishing (CMP) processes are conducted to remove materials on backside of the wafer, then material removal is achieved, but uneven flatness and misalignment during bonding occur

Engineering Contradiction:
Improvematerial removalVSAvoidflatness and alignment
Core Design Contradiction:
Loss of substanceVSManufacturing precision

Solution Approach 1:

The wafer is divided into a device wafer and a blanket wafer that are bonded together. The blanket wafer serves as a separate substrate that can be independently processed and removed later, allowing the device wafer to maintain its structural integrity and flatness without undergoing aggressive CMP processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Materials are removed from the blanket wafer before bonding to the device wafer, rather than after bonding. This preliminary removal avoids the need for post-bonding CMP on the device wafer, preventing damage to already-bonded structures and maintaining alignment precision.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If anneal process is performed to separate the blanket wafer, then separation into portions is achieved, but thermal budget increases

Engineering Contradiction:
Improveseparation precisionVSAvoidthermal budget
Core Design Contradiction:
Manufacturing precisionVSTemperature

Solution Approach 1:

The annealing process parameters (temperature, time, atmosphere) are optimized to achieve complete separation of the blanket wafer into removable portions while maintaining the thermal budget within acceptable limits for the device wafer. The process is controlled to prevent excessive heat exposure that could damage temperature-sensitive devices.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If conventional bonding methods are used, then wafer bonding is achieved, but misalignment and flatness issues reduce bonding quality

Engineering Contradiction:
Improvebonding qualityVSAvoidalignment and flatness
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The blanket wafer is prepared in advance by removing materials and creating a flat, clean bonding surface before bonding to the device wafer. This preliminary preparation ensures optimal bonding conditions and eliminates the need for post-bonding alignment corrections.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The blanket wafer acts as an intermediary substrate that facilitates the bonding process. It provides a stable, easily processable platform that can be bonded to the device wafer without requiring the device wafer itself to undergo aggressive processing that would compromise its flatness or alignment.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the flatness and alignment of bonded wafers, reducing thermal budget requirements and enabling effective integration of semiconductor devices while maintaining low operating voltage and power consumption.

Implementation Method 1

part of the second wafer includes a doped region formed by hydrogen ion implantation

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

performing an anneal process to separate the second wafer into a first portion and a second portion

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 3

performing an anneal process to separate the second wafer into a first portion and a second portion

Methodology Applied
Scientific EffectThermal diffusion: Diffusion

Data Source

PatentUS20240072097A1Semiconductor device and method for fabricating the same
Publication Date: 2024.02.29 UNITED MICROELECTRONICS CORP
  • US20240072097A1 patent drawing
  • US20240072097A1 patent drawing
  • US20240072097A1 patent drawing

AI summary

A method for fabricating a semiconductor device includes the steps of providing a first wafer and a second wafer as the first wafer includes a device wafer and the second wafer includes a blanket wafer, bonding the first wafer and the second wafer, performing a thermal treatment process to separate the second wafer into a first portion and a second portion, and then planarizing the first portion.