Wafer-on-Wafer Semiconductor Packaging to Cut Gapfill Processing
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Solution Overview
Problem
The increasing complexity of integrated circuits has led to higher manufacturing costs and longer cycle times due to the need for individual die preparation and gapfill processing in forming semiconductor packages.
Innovation Solution
The wafer-on-wafer bonding process allows for the direct bonding of device wafers to form a wafer-on-wafer-on-wafer (WoWoW) structure, which is then singulated into individual semiconductor packages, eliminating the need for gapfill processing and reducing manufacturing costs and cycle times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual die preparation and gapfill processing are performed for each die, then manufacturing precision and reliability are improved, but manufacturing cost and cycle time increase
Solution Approach 1:
The patent merges multiple individual die processing steps into a single wafer-level operation. By bonding entire wafers together before singulation, the process eliminates the need for separate gapfill processing and individual die preparation for each die, thereby reducing cycle time while maintaining reliability through consistent wafer-level bonding conditions
Solution Approach 2:
The patent performs wafer bonding as a preliminary action before singulation into individual dies. This preliminary wafer-level bonding allows subsequent gapfill and packaging operations to be performed on the entire wafer array simultaneously, rather than processing each die individually after separation, thus reducing overall manufacturing cycle time
2Reliability
If individual die preparation and gapfill processing are performed for each die, then manufacturing precision and reliability are improved, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple individual die processing steps into a single wafer-level operation. By bonding entire wafers together before singulation, the process eliminates the need for separate gapfill processing and individual die preparation for each die, thereby reducing cycle time while maintaining reliability through consistent wafer-level bonding conditions
Solution Approach 2:
The wafer-level bonding process serves multiple functions simultaneously: it bonds multiple dies to multiple substrates in parallel, enables subsequent gapfill operations on entire wafer arrays, and maintains consistent bonding conditions across all dies. This multi-functionality reduces both cost and cycle time compared to individual die processing
3Device complexity
If wafer-on-wafer bonding is performed without removing the first carrier wafer, then process complexity is reduced, but singulation precision deteriorates
Solution Approach 1:
The patent extracts and removes the first carrier wafer from the bonded wafer structure before performing singulation. This removal eliminates the carrier wafer as an interfering element during the singulation process, allowing precise sawing or cutting through the bonded device wafer and substrate without encountering the carrier wafer, thus maintaining high singulation precision
Solution Approach 2:
The patent performs carrier wafer removal as a preliminary action before singulation. This preliminary removal of the first carrier wafer prepares the bonded structure for precise singulation by eliminating potential interference, allowing subsequent singulation to proceed with high precision while keeping the overall process relatively simple
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and cycle times by eliminating the need for individual die preparation and gapfill processing, while also improving the reliability of integrated circuit manufacturing.
Implementation Method 1
bonding a first device wafer to a first carrier wafer
Implementation Method 2
bonding a second device wafer to the first device wafer
Implementation Method 3
bonding a third device wafer to the second device wafer
Data Source
AI summary
A wafer on wafer on wafer and a chip on wafer on wafer structure and methods of forming the same are provided. In accordance with some embodiments, a first device wafer is bonded to a first carrier through wafer-on-wafer bonding and additional device wafers may subsequently be bonded to the first device wafer. A support wafer is then bonded to the top most device wafer and the first wafer may then be removed. The bonded wafer structure may then be singulated into individual semiconductor device packages. Through the wafer-on-wafer bonding process, the manufacturing cost and cycle time may be reduced.