Wafer Bonding Misalignment Detection via Test Patterns
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Solution Overview
Problem
The challenge in semiconductor technology is to improve the reliability of memory devices by detecting and mitigating wafer misalignment failures during the bonding process, which affects the manufacturing yield and increases the risk of voltage drops due to contact resistance in partially misaligned bonding pads.
Innovation Solution
A memory device with a test pattern comprising test pads on multiple wafers allows for the detection of misalignment failures by applying a test signal and measuring the output signal, enabling the identification of misalignment issues and providing a boost voltage to compensate for voltage drops, thus improving manufacturing reliability and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If elements are fabricated on separate wafers and bonded together to reduce occupation area, then the area of the memory device is reduced, but the risk of wafer misalignment failures increases
Solution Approach 1:
The patent applies preliminary action by incorporating test patterns and test pads during the wafer fabrication process before bonding occurs. These test structures are pre-configured to enable subsequent detection of misalignment failures, allowing the system to identify and mitigate reliability issues that arise from the multi-wafer bonding approach used to reduce occupation area.
2Reliability
If wafer misalignment detection is implemented, then the reliability of the memory device is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent merges the test pattern structures with the existing circuit elements and bonding pad structures during wafer fabrication. The test pads are integrated into the same fabrication layers and processes as the functional bonding pads, combining testing functionality with existing manufacturing steps rather than adding separate, complex testing infrastructure.
3Productivity
If additional test patterns are added to detect misalignment, then the manufacturing yield is improved, but the manufacturing time increases
Solution Approach 1:
The test patterns are configured and prepared during the wafer fabrication process itself, before bonding occurs. This preliminary configuration allows misalignment detection to be performed immediately after bonding without requiring separate testing cycles, thereby improving manufacturing yield while minimizing additional manufacturing time.
4Reliability
If misalignment detection is performed, then voltage drops due to contact resistance are prevented, but the device complexity increases
Solution Approach 1:
The test patterns serve as intermediary structures that enable indirect detection of misalignment issues affecting bonding pad contact resistance. Rather than directly measuring contact resistance at the bonding interface, the test patterns provide accessible test points that reveal misalignment conditions through electrical continuity testing, preventing voltage drops without adding complex direct measurement mechanisms.
Data Source
AI summary
A memory device includes a first wafer including a first bonding pad disposed on a first surface; a second wafer, including a second bonding pad disposed on a second surface of the second wafer, the second surface of the second wafer bonded on the first surface of the first wafer; and a first test pattern. The first test pattern includes a pair of first test pads disposed on the first surface and electrically coupled to each other; a pair of second test pads disposed on the second surface of the second wafer and respectively coupled to the pair of first test pads, when no misalignment failure between the first bonding pad and the second bonding pad occurs; and a pair of third test pads disposed on a third surface of the second wafer, which is opposite to the second surface, and respectively coupled to the pair of second test pads.