Wafer Bonding for High-Resolution Optoelectronic Device Assembly

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Solution Overview

Problem

The existing methods for manufacturing optoelectronic devices, such as display screens, require complex alignment and increased manufacturing time due to the small size of light-emitting diodes, and the use of thin film transistors limits the scalability and efficiency of high-resolution video display.

Innovation Solution

A method involving the formation of three-dimensional light-emitting diodes with molecular bonding of metal layers and insulated conductive trenches to integrate control electronics directly under the display pixels, eliminating the need for complex alignment and enabling efficient assembly of high-resolution displays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the pick-and-place method is used to manufacture optoelectronic devices with small light-emitting diodes, then the device can be assembled, but the alignment becomes increasingly complex as dimensions decrease

Engineering Contradiction:
Improveease of assemblyVSAvoidalignment precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent segments the device into two separately manufactured wafers (first wafer with electronic components, second wafer with light-emitting diodes) that are subsequently bonded together. This segmentation allows each wafer to be manufactured independently with optimized processes, avoiding the need for complex alignment during assembly of miniaturized components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar assembly to three-dimensional integration by bonding two wafers together vertically. The metal layers are formed on opposite surfaces of the two wafers, and bonding occurs in the vertical dimension, eliminating the need for precise lateral alignment of miniaturized components.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Measurement precision

If the resolution of the optoelectronic device is increased, then the display quality improves, but the number of transfers of light-emitting diodes increases and manufacturing duration increases

Engineering Contradiction:
Improvedisplay resolutionVSAvoidmanufacturing speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent segments the manufacturing process into parallel wafer fabrication steps followed by a single bonding operation. Multiple light-emitting diodes are manufactured on the second wafer simultaneously, and multiple electronic components are manufactured on the first wafer simultaneously, then both wafers are bonded in one step, dramatically reducing the number of transfers required for high-resolution displays.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary manufacturing of arrays of light-emitting diodes and electronic components on separate wafers before final assembly. This preliminary action allows large numbers of components to be prepared in parallel, and the subsequent bonding step efficiently combines them without requiring individual transfers, thus maintaining high manufacturing speed despite high resolution requirements.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If control circuits are assembled with light-emitting diodes and coupled by wires, then the device can be controlled, but the quantity of data transmitted decreases and video stream display becomes difficult

Engineering Contradiction:
Improvecontrol capabilityVSAvoiddata transmission capacity
Core Design Contradiction:
Ease of operationVSLoss of information

Solution Approach 1:

The patent merges the control circuits and light-emitting diodes into a single integrated structure by bonding the first wafer (with control circuits) directly to the second wafer (with light-emitting diodes) through metal layers. This integration eliminates the need for wire coupling, reduces parasitic inductance and resistance, and enables high-speed data transmission required for video stream display.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from lateral wire coupling to vertical integration through wafer bonding. The control circuits and light-emitting diodes are connected in the vertical dimension through bonded metal layers, enabling direct and efficient signal transmission without the limitations of wire-based coupling in the lateral dimension.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the efficient manufacturing of high-resolution optoelectronic devices with integrated control electronics, reducing manufacturing time and enabling scalable production of high-resolution displays without the need for thin film transistors.

Implementation Method 1

placing into contact the first and second metal layers to bond them by molecular bonding

Methodology Applied
Scientific EffectMolecular bonding: Chemical Bonding

Data Source

PatentUS11581295B2Optoelectronic device
Publication Date: 2023.02.14 ALEDIA INC
  • US11581295B2 patent drawing
  • US11581295B2 patent drawing
  • US11581295B2 patent drawing

AI summary

A method of manufacturing an optoelectronic device, including the steps of: forming, on a first surface of a first including assemblies of electronic components, a stack of insulating layers and of conductive tracks; forming, on another wafer, light-emitting diodes each comprising ends; forming a metal layer on at least a portion of the surface of the first wafer and another metal layer on at least a portion of the surface of the second wafer, the other metal layer being electrically coupled to the end of each light-emitting diode; placing into contact the metal layers; forming an insulated conductive via connecting another surface of the wafer to a conductive track; and forming insulated conductive trenches surrounding diodes.