Wafer Bonding Structure Using Package Pad Layers
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Solution Overview
Problem
The existing Through Silicon Via (TSV) technology, used for wafer-level packaging, becomes complex and prone to process problems when integrating multiple wafer stacks, leading to issues like cold solder joints, broken connections, and damaged pads during the bonding process.
Innovation Solution
A bonding structure and method that form a chip stack by sequentially bonding multiple wafers using package pad layers, eliminating the need for via holes by electrically connecting the first package pad layer of the chip stack to a second package pad layer on a substrate, thereby simplifying the manufacturing process and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSV technology is used for wafer-level packaging, then vertical interconnection between wafers is achieved, but the manufacturing process becomes complex and process problems occur when integrating more than two wafers
Solution Approach 1:
The patent segments the wafer bonding process into discrete stages: forming package pad layers on each wafer, sequential bonding of multiple wafers, and post-bonding processing. This segmentation allows each wafer to be processed and bonded independently, reducing the complexity of integrating multiple wafers compared to traditional TSV methods that require complex through-hole formation and filling processes for the entire stack.
Solution Approach 2:
The package pad layers are formed on the wafers before bonding occurs. This preliminary action prepares the bonding surfaces in advance, ensuring that electrical connections are established through the pad layers rather than requiring complex via hole formation and conductive material filling during the bonding process itself, thereby simplifying the overall manufacturing process.
2Reliability
If TSV technology is used for packaging multiple wafers, then vertical interconnection is achieved, but defects such as cold solder joints, broken connections, and damaged pads occur
Solution Approach 1:
The package pad layers serve as intermediary elements between the wafers during bonding. These pad layers provide a controlled interface for electrical connections, replacing the direct metal-to-metal connections required in TSV technology. This intermediary structure reduces the occurrence of bonding defects such as cold solder joints and broken connections by providing a more forgiving bonding interface that can accommodate minor misalignments and surface variations.
3Reliability
If via holes are formed and filled with conductive materials to achieve vertical interconnection, then inter-wafer connectivity is established, but the manufacturing process becomes complex and prone to errors
Solution Approach 1:
The patent extracts the electrical connection function from the complex TSV process (via hole formation and conductive material filling) and relocates it to the package pad layers formed on the wafer surfaces. This extraction eliminates the need for complex via hole processing while maintaining the essential function of electrical interconnection between wafers, thereby improving ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process and enhances the reliability of chip stacks by eliminating the need for via holes, reducing the complexity of bonding multiple wafers and minimizing defects such as cold solder joints and broken connections.
Implementation Method 1
bonding the two wafers by the bonding layer
Implementation Method 2
performing thinning from the second surface of the wafer by an acid etching
Implementation Method 3
performing a planarization of the second surface of the wafer by a chemical mechanical polishing
Data Source
AI summary
A bonding structure and a method for manufacturing the bonding structure are provided. Multiple chips arranged in an array are formed on a surface of a wafer. Each of the chips includes a device structure, an interconnect structure electrically connected to the device structure, and a first package pad layer electrically connected to the interconnect structure. The first package pad layer is arranged at an edge region of the chip. A chip stack is obtained after bonding and cutting the multiple wafers, and the first package pad layer at the edge region of the chip is exposed.