Hybrid Wafer Bonding Structure for Vertical Metal Pad Expansion

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Solution Overview

Problem

In hybrid wafer bonding, existing technologies face challenges in ensuring sufficient thermal expansion of metal pads during the annealing process, leading to potential disconnections and reduced productivity due to differences in material properties and thermal expansion coefficients between dielectric layers and metal pads.

Innovation Solution

A bonding structure incorporating a multi-layered dielectric layer with a vertical expansion inducing layer, such as silicon nitride and silicon carbon nitride, is used to apply stress to metal pads, facilitating their thermal expansion in the vertical direction and enhancing bonding between wafers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a single-layer dielectric structure is used, then the structure is simple, but the metal pad cannot expand sufficiently in the vertical direction during thermal annealing

Engineering Contradiction:
Improvevertical expansion of metal padVSAvoiddielectric layer structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The dielectric layer is divided into multiple sub-layers (first dielectric layer, second dielectric layer, third dielectric layer) with different material compositions and hardness values. This segmentation allows each layer to contribute differently to the overall stress distribution, enabling controlled vertical expansion of the metal pad while maintaining structural integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the dielectric structure are assigned different material properties - the first dielectric layer has higher hardness to provide strong stress concentration at the bonding interface, while lower layers have progressively lower hardness to allow controlled deformation. This local differentiation of material quality optimizes the expansion mechanism.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If the dielectric layer is too hard, then it provides strong stress for expansion, but it causes lateral deformation of the metal pad

Engineering Contradiction:
Improvevertical expansion controlVSAvoidlateral deformation of metal pad
Core Design Contradiction:
Manufacturing precisionVSShape

Solution Approach 1:

The dielectric structure is segmented into multiple layers with a gradient of hardness values. The highest hardness layer is positioned only at the bonding interface where vertical stress is needed, while lower hardness layers are positioned deeper to accommodate lateral deformation without causing damage. This segmentation separates the stress application function from the deformation constraint function.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The hardness parameter of the dielectric material is changed progressively across different layers. The first dielectric layer has higher hardness to generate strong vertical stress, while subsequent layers have lower hardness values that increase progressively, allowing the structure to transition from rigid stress application to flexible deformation accommodation.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If thermal annealing is performed without proper stress control, then the process is simple, but disconnections occur between bonded wafers

Engineering Contradiction:
Improvebonding reliabilityVSAvoidbonding structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The multi-layer dielectric structure is prepared in advance with specific hardness gradients and material compositions before the bonding process. This preliminary structuring creates built-in stress distribution characteristics that automatically guide the thermal expansion behavior during annealing, ensuring reliable bonding without requiring complex real-time control during the actual bonding process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dielectric structure uses composite materials with different mechanical and thermal properties arranged in specific layers. This composite structure combines materials with high hardness for stress generation and materials with lower hardness for deformation accommodation, creating a synergistic system that ensures reliable bonding through controlled stress distribution during thermal annealing.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach prevents disconnections and improves the electrical bonding between metal pads, increasing the productivity of semiconductor devices by ensuring reliable thermal expansion and bonding without lateral deformation.

Implementation Method 1

The metal pads of the wafers may be directly contacted by thermal expansion using an annealing process

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 2

The metal pads of the wafers may be directly contacted by thermal expansion using an annealing process

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20240413109A1Bonding structure for a hybrid wafer bonding, semiconductor device including the bonding structure and method of manufacturing the semiconductor device
Publication Date: 2024.12.12 SK HYNIX INC
  • US20240413109A1 patent drawing
  • US20240413109A1 patent drawing
  • US20240413109A1 patent drawing

AI summary

A bonding structure for a hybrid wafer bonding may include a plurality of bonding pads and a bonding insulation layer. The bonding insulation layer may be configured to electrically isolate the bonding pads from each other. The bonding insulation layer may include at least one dielectric layer and a vertical expansion inducing layer arranged on the dielectric layer. The vertical expansion inducing layer including a hardness greater than a hardness of the dielectric layer.