Wafer Bonding Pad Layout to Prevent 3D Memory Delamination
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Solution Overview
Problem
Existing semiconductor devices with 3D memory structures face challenges in achieving strong bonding forces during the wafer bonding process, which can lead to delamination issues.
Innovation Solution
The semiconductor device incorporates first and second bonding pads formed in the scribe lane areas of the first and second structures, respectively, which are made of the same material and designed to increase the bonding force between the structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wafer bonding method is used to combine first wafer with peripheral circuit and second wafer with memory cells, then integration degree is improved, but bonding force is insufficient causing delamination
Solution Approach 1:
The patent introduces bonding pads as intermediary elements between the first and second wafers. These bonding pads are specifically designed with the same material composition to facilitate strong bonding. The bonding pads act as mediators that enhance the bonding force between the wafers, preventing delamination while maintaining the wafer bonding method for high integration.
Solution Approach 2:
The patent applies homogeneity by forming bonding pads from the same material as the existing structures on the wafers. This material uniformity ensures compatible bonding characteristics and strong adhesion between the bonded wafers, resolving the bonding force insufficiency issue while preserving the integration benefits of the wafer bonding approach.
2Strength
If bonding pads are formed in scribe lane area using same material, then bonding force is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the bonding pad formation process with the existing scribe lane area processing. By utilizing the scribe lane area (which is already prepared for peripheral circuits) and forming bonding pads using the same material as existing structures, the patent combines multiple functions into existing process steps, thereby improving bonding force without significantly increasing manufacturing complexity.
Data Source
AI summary
Provided herein may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a first structure including a first chip area and a first scribe lane area, a second structure provided on the first structure, a first alignment key disposed in the first scribe lane area, at least one first bonding pad provided between the first alignment key and the first chip area, the first bonding pad bordering an upper surface of the first structure, and a second bonding pad bordering a lower surface of the second structure to contact the at least one first bonding pad.