Wafer Scale Supercomputer Face-to-Face Bonding Power Delivery
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Solution Overview
Problem
Wafer-scale computing devices face challenges in maintaining adequate supply voltage levels during power transients and require modifications to semiconductor manufacturing processes, especially with limited space for capacitors due to smaller laminate substrates compared to standard chip packaging.
Innovation Solution
Face-to-face bonding of two wafers, where one wafer with conventional kerf and crack-stop structures is bonded with another wafer providing interconnects and featuring thru silicon vias and edge seal moisture barriers, allowing for efficient electrical connections and power delivery without the need for additional capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-scale packaging with smaller laminate substrates is used, then device integration is improved, but space for capacitors is reduced
Solution Approach 1:
The patent transitions from planar capacitor placement on the laminate substrate to vertical 3D stacking with wafer-to-wafer bonding. Capacitors are placed on the back side of the first wafer or integrated within the wafer stack, utilizing the third dimension (vertical space) rather than competing for limited lateral substrate area. This enables high integration while maintaining adequate capacitor space through spatial reorganization.
2Reliability
If face-to-face wafer bonding is implemented, then electrical connections between chips are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent performs wafer bonding before dicing the wafers into individual chips. All electrical interconnections, vias, and wiring are established at the wafer level while the chips are still attached to the carrier wafer. This preliminary action simplifies manufacturing because the bonding surfaces are larger and easier to align, and subsequent dicing automatically preserves the pre-established connections without requiring complex post-dicing assembly operations.
3Adaptability or versatility
If crack-stop structures are removed for wiring, then chip-to-chip stitching is enabled, but moisture barrier effectiveness is reduced
Solution Approach 1:
The patent moves the moisture barrier function from the lateral plane (crack-stop structures around chip perimeters) to the vertical dimension (edge seal around the entire wafer perimeter). The edge seal provides comprehensive moisture protection at the wafer level, eliminating the need for peripheral crack-stop structures that would interfere with chip-to-chip wiring. This dimensional shift enables both robust moisture barrier and flexible interconnectivity.
4Reliability
If edge seal moisture barrier is introduced, then moisture protection is improved, but manufacturing modifications are increased
Solution Approach 1:
The patent combines the edge seal moisture barrier formation with the existing wafer bonding process flow. The edge seal is integrated into the wafer fabrication process before bonding, utilizing the same processing steps and materials already present in the manufacturing line. This merging approach provides comprehensive moisture protection without requiring separate, complex manufacturing modifications, as the edge seal becomes an inherent part of the wafer structure rather than an add-on feature.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables effective electrical connections and power delivery between chip sites, maintaining stable voltage levels during power transients while minimizing modifications to the semiconductor manufacturing process, particularly for advanced node technologies.
Implementation Method 1
the first wafer and the second wafer are bonded face-to-face such that the interconnect structures of the second wafer electrically connect adjacent chip sites of the first wafer
Data Source
AI summary
A data processing system includes a first wafer comprising a plurality of first chips, and kerf and crack-stop structures around perimeters of the first chips, and a second wafer comprising a plurality second chips, a plurality of interconnect structures through a connection zone between the second chips, and a plurality of thru silicon vias, wherein the first wafer and the second wafer are bonded face-to-face such that the interconnect structures of the second wafer electrically connect adjacent chip sites of the first wafer and where a pitch of the chips on the first and second wafer are equal.