Piezoelectric Wafer Bonding with Peripheral Relief Removal

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Solution Overview

Problem

The existing processes for bonding a piezoelectric substrate to a carrier substrate result in defects such as voids at the periphery due to differences in thermal expansion coefficients and the trapping of condensation water, leading to poor bonding quality.

Innovation Solution

A process involving chemical mechanical polishing followed by removal of peripheral matter on the polished surfaces to planarize the bonding interfaces, using ion beam milling for precise control, and optionally forming a weakened region for controlled detachment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If chemical mechanical polishing is performed on the bonding surfaces, then surface flatness is improved, but peripheral relief is generated causing bonding voids

Engineering Contradiction:
Improvesurface flatnessVSAvoidbonding quality
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent removes the peripheral relief generated by chemical mechanical polishing through selective etching or mechanical removal at the periphery of the substrate. This extraction of the problematic peripheral material eliminates the source of bonding voids while preserving the flat central bonding surface.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies different treatments to different regions of the substrate: the central bonding surface is polished for flatness, while the periphery is selectively removed or treated differently to eliminate relief. This local differentiation resolves the contradiction between achieving overall flatness and preventing peripheral bonding defects.

Inventive Principle:
Principle #3Local quality

2Strength

If thermal oxidation is used to form oxide layers for bonding, then adhesion is improved, but compatibility with certain materials is reduced and diffusion is hindered

Engineering Contradiction:
ImproveadhesionVSAvoidmaterial compatibility
Core Design Contradiction:
StrengthVSAdaptability or versatility

Solution Approach 1:

The patent changes the formation method of the oxide layer from thermal oxidation to plasma-enhanced chemical vapor deposition (PECVD). This parameter change in the deposition process allows for lower temperatures and better compatibility with sensitive materials like polycrystalline silicon, while still achieving adequate adhesion for bonding.

Inventive Principle:
Principle #35Parameter changes

3Strength

If consolidation annealing is performed to strengthen oxide-oxide bonding, then bond strength is improved, but assembly deformation increases due to thermal expansion differences

Engineering Contradiction:
Improvebond strengthVSAvoidassembly deformation
Core Design Contradiction:
StrengthVSShape

Solution Approach 1:

The patent reduces the consolidation annealing temperature from the conventional 100-300°C range to below 100°C, or eliminates it entirely by optimizing the oxide layer deposition parameters. This parameter change in temperature prevents excessive thermal stress and deformation while maintaining adequate bond strength through improved oxide layer quality from PECVD deposition.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improves bonding quality by eliminating peripheral relief and condensation water, reducing voids and enhancing the stability of the multilayer structure under thermal stress.

Implementation Method 1

removal of peripheral matter on the polished surfaces to planarize the bonding interfaces, using ion beam milling for precise control

Methodology Applied
Scientific EffectIon beam milling: Ion Beam

Implementation Method 2

chemical mechanical polishing followed by removal of peripheral matter on the polished surfaces

Methodology Applied
Scientific EffectChemical mechanical polishing:

Data Source

PatentUS20260020498A1Process for fabricating a piezoelectric or semiconductor structure
Publication Date: 2026.01.15 SOITEC SA
  • US20260020498A1 patent drawing
  • US20260020498A1 patent drawing
  • US20260020498A1 patent drawing

AI summary

A process for fabricating a semiconductor or piezoelectric structure comprises the following successive steps: (a) providing a donor substrate comprising a piezoelectric or semiconductor layer, (b) providing a receiver substrate, (c) treating a free surface of the donor substrate and/or a free surface of the receiver substrate, (d) bonding the donor substrate to the receiver substrate, the at least one treated free surface being at the interface between the donor substrate and the receiver substrate, and (e) transferring a portion of the piezoelectric or semiconductor layer from the donor substrate to the receiver substrate. The treatment of the free surface of the donor substrate and/or of the free surface of the receiver substrate comprises the following successive steps: (c1) chemical-mechanical polishing, and (c2) removing material from a peripheral region of the polished surface.