Wafer Bonding Strength Pattern for Precise 3D Chip Stacking
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Solution Overview
Problem
The semiconductor industry faces challenges in further reducing minimum feature size due to process limitations, which hinders continued improvement in integration density.
Innovation Solution
A method of fabricating a semiconductor chip involves forming a bonding material layer on a first wafer substrate with a strength adjustment pattern, bonding a second wafer substrate with a semiconductor component layer to the first wafer substrate, and adjusting the bonding strength by controlling the area of the strength adjustment pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bonding strength is increased to prevent wafer peeling, then the bonding reliability is improved, but the risk of misalignment and fabrication precision loss increases
Solution Approach 1:
The bonding layer is designed with non-uniform thickness, creating regions of strong bonding and regions of weak bonding. The first region has bonding layer thickness within 50-200 nm for strong bonding, while the second region has bonding layer thickness within 200-500 nm for weak bonding. This local variation in bonding strength allows the wafer to maintain overall bonding reliability while providing specific areas that accommodate stress and prevent misalignment during fabrication processes.
2Productivity
If the minimum feature size is reduced to improve integration density, then the integration density is improved, but process limitations make further reduction difficult
Solution Approach 1:
Instead of continuing to reduce minimum feature size in the lateral dimension, the invention transitions to optimizing bonding layer thickness in the vertical dimension. By controlling bonding layer thickness within specific ranges (50-200 nm for strong bonding regions, 200-500 nm for weak bonding regions), the invention achieves improved integration density through vertical dimension optimization while avoiding the process limitations that constrain further lateral feature size reduction.
Data Source
AI summary
A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.