Stress Compensation Layer for Wafer Bonding Distortion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Wafer bonding technologies often result in non-uniformly distributed in-plane distortions (IPD) and stresses in wafers, which existing solutions fail to completely eliminate, leading to residual distortions of 10-100 nm.
Innovation Solution
A stress compensation layer with a non-uniformly distributed stress field, composed of materials like Si3N4 or SiO2 with ion impurities, is applied to the wafers to complement and compensate the stress field, ensuring an even distribution of stress across the bonded wafers without requiring significant changes to bonding tools or processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wafer bonding is performed by locally deforming wafers to make local contact, then bonding is initiated, but undesirable distortions and stress are introduced in the wafers
Solution Approach 1:
The patent applies parameter changes by modifying the stress field distribution through ion implantation. Different regions of the wafer are implanted with different ion doses or types, changing the mechanical stress parameters locally to compensate for bonding-induced distortions while maintaining bonding reliability
Solution Approach 2:
The patent implements preliminary anti-action by pre-applying a compensatory stress field to the wafer before bonding. This pre-stress counteracts the expected bonding-induced stress, preventing distortions before they occur during the bonding process
2Manufacturing precision
If existing solutions are used to reduce wafer bonding distortion, then some distortion reduction is achieved, but residual distortions of 10-100 nm remain
Solution Approach 1:
The patent applies local quality by creating spatially varying stress compensation zones across the wafer surface. Different regions receive tailored ion implantation parameters (dose, energy, type) to address local distortion patterns, achieving comprehensive correction down to 10-100 nm residual levels
Solution Approach 2:
The patent uses composite material approaches by combining multiple ion species or varying ion implantation parameters across different wafer regions. This creates a composite stress field distribution that more effectively compensates for complex distortion patterns
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress compensation layer effectively corrects non-uniformly distributed stress fields, achieving a substantially uniform stress distribution across the wafers, thereby reducing distortions and improving the accuracy of subsequent processing steps.
Implementation Method 1
The stress compensation layer includes a first material at a first location of the stress compensation layer overlapping with the first location of the first wafer, a second material at a second location of the stress compensation layer overlapping with the second location of the first wafer. The stress compensation layer induces a third stress level at the first location of the first wafer, and a fourth stress level at the second location of the first wafer
Data Source
AI summary
Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.


