Wafer Bonding Support Structure for 3D IC Stress Reduction

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Solution Overview

Problem

The semiconductor industry faces challenges in stacking two-dimensional (2D) ICs into three-dimensional (3D) ICs due to non-bond areas over the peripheral regions of wafers, which result in inadequate structural support and mechanical stress during bonding and processing, leading to mechanical failures and reduced yield.

Innovation Solution

The formation of bonding support structures, such as layers of dielectric material, over the peripheral regions of semiconductor wafers to reduce non-bond areas by creating a substantially planar surface, thereby improving structural support and reducing mechanical stress during bonding and subsequent processing steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If wafer stacking is performed without bonding support structures, then the stacking process can be simplified, but non-bond areas over peripheral regions result in inadequate structural support and mechanical stress

Engineering Contradiction:
Improvebonding support structureVSAvoidstructural support
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The bonding support structure is formed in advance over the peripheral regions of the wafer before the bonding process. This preliminary action ensures that when stacking occurs, the peripheral regions already have adequate structural support to handle mechanical stresses, preventing bonding failures and improving overall reliability without complicating the stacking process itself

Inventive Principle:
Principle #10Preliminary action

2Reliability

If bonding support structures are formed over peripheral regions, then structural integrity is improved, but the manufacturing process becomes more complex

Engineering Contradiction:
Improvebonding yieldVSAvoidmanufacturing process
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The bonding support structure is segmented to be formed only over the peripheral regions of the wafer, not the entire surface. This selective formation approach improves bonding yield by providing support where it is most needed (at the edges where stress concentrates) while minimizing the additional manufacturing complexity by limiting the structure to specific areas rather than requiring complete wafer modification

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If peripheral regions are left without bonding support, then the manufacturing process is simpler, but mechanical stress during bonding leads to failures

Engineering Contradiction:
Improveprocessing simplicityVSAvoidmechanical stress
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The bonding support structure acts as an intermediary element between the peripheral regions of the wafer and the bonding process. It mediates the mechanical stresses that occur during bonding and subsequent processing by providing a supportive foundation that distributes and absorbs stress, preventing direct transmission of harmful forces to the bonded interfaces while maintaining overall process simplicity

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11139210B2Bonding support structure (and related process) for wafer stacking
Publication Date: 2021.10.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11139210B2 patent drawing
  • US11139210B2 patent drawing
  • US11139210B2 patent drawing

AI summary

In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.