Semiconductor Wafer Bonding with Non-Contact Test Pad Layout
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Solution Overview
Problem
The yield of semiconductor chips decreases due to defects in chip areas during the bonding of wafers, leading to inefficiencies in the manufacturing process.
Innovation Solution
A semiconductor device is manufactured by bonding a circuit wafer with an array wafer and another array wafer, utilizing test pads that are not in contact with the bonding interfaces to facilitate testing and reduce defects, thereby increasing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafers are bonded to manufacture semiconductor chips, then productivity is improved through batch processing, but yield decreases due to defects in chip areas
Solution Approach 1:
The patent performs testing on wafers before bonding to identify and isolate defective chip areas. By conducting preliminary testing and creating isolation structures (such as trenches or insulation layers) around defective regions before the bonding process, the defect propagation is prevented. This allows the bonding process to proceed with higher overall yield since defective areas are contained and do not compromise adjacent functional chips.
2Measurement precision
If testing is performed on all pads during wafer bonding, then measurement precision is improved, but device complexity increases due to additional test structures
Solution Approach 1:
The patent applies different treatments to different pads based on their testing results. Instead of uniformly treating all pads, the method identifies pads with defects through preliminary testing and applies isolation structures only to those specific locations. This localized approach maintains measurement precision for defect detection while avoiding the addition of test structures across the entire wafer, thereby reducing overall device complexity.
3Reliability
If defective chip areas are isolated after bonding, then yield is improved by salvaging functional chips, but manufacturing precision decreases due to additional processing steps
Solution Approach 1:
The patent performs the opposite of post-bonding isolation by conducting preliminary testing before bonding and creating isolation structures in advance. This preliminary isolation approach allows the bonding process to proceed without interference from defective areas, maintaining bonding interface quality. The isolation structures are created while the wafer is still accessible, enabling precise fabrication before the bonding process begins.
Data Source
AI summary
In one embodiment, a semiconductor device includes a first interconnect including a first pad. The semiconductor device further includes a second pad provided on the first interconnect. In the semiconductor device, the second pad is in contact with another pad, and the first pad is not in contact with another pad.