Wafer Bonding Structure for Nanogap-Free Through-Via Coupling
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Solution Overview
Problem
Existing semiconductor fabrication processes face inefficiencies and failures during wafer-to-wafer bonding due to nanogaps and misalignment issues, leading to incomplete coupling of wiring lines between bonded wafers.
Innovation Solution
A semiconductor device with a wafer-to-wafer bonding structure that includes a through via passing through multiple dielectric layers and isolation layers, enhancing the contact area and coupling force between wafers, thereby preventing misalignment and nanogap-related failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wafer-to-wafer bonding is used, then fabrication process is simpler, but nanogaps and misalignment occur leading to bonding failures
Solution Approach 1:
The patent introduces a bonding assistance pattern as an intermediary element between the first and second wafers. This pattern includes a first bonding assistance pattern on the first wafer and a second bonding assistance pattern on the second wafer, which facilitate precise alignment and stable bonding. The intermediary pattern acts as a reference structure that eliminates nanogaps and prevents misalignment during the bonding process, thereby improving bonding reliability without significantly increasing overall device complexity.
2Reliability
If through via is added to pass through multiple layers, then electrical coupling stability improves, but manufacturing complexity increases
Solution Approach 1:
The patent forms the through via structure in advance during the fabrication process, before final bonding occurs. The through via is created by sequentially forming holes through the first dielectric layer, second dielectric layer, and third dielectric layer, and filling them with conductive material. This preliminary formation of the through via ensures that electrical coupling pathways are established beforehand, improving coupling stability while allowing the via to be integrated into the existing fabrication flow.
3Manufacturing precision
If multiple dielectric layers and isolation layers are used, then misalignment prevention improves, but device structure becomes more complex
Solution Approach 1:
The patent divides the bonding structure into multiple functional layers: a first dielectric layer, a second dielectric layer, and a third dielectric layer, each serving specific purposes. The first dielectric layer provides initial isolation and support, the second dielectric layer provides additional isolation and structural support, and the third dielectric layer provides final isolation and support. This segmentation of functions into distinct layers enables precise alignment and misalignment prevention while maintaining a manageable layer structure through clear functional differentiation.
Data Source
AI summary
A method for manufacturing a semiconductor device comprises: forming isolation layers in a front surface of an upper wafer substrate; forming a through hole that exposes one of the isolation layers, through the upper wafer substrate from a back surface of the upper wafer substrate; forming a first dielectric layer that fills the through hole; defining a lower wafer including a lower wafer substrate, a second dielectric layer defined on the lower wafer substrate, and a first wiring line disposed in the second dielectric layer; bonding a top surface of the second dielectric layer and a bottom surface of the first dielectric layer; forming a third dielectric layer on the front surface of the upper wafer substrate; forming a through via that passes through the third dielectric layer, the one isolation layer, the first dielectric layer; and forming a second wiring line coupled to the through via.