Wafer Bow Control via Backside Stress Compensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor wafers experience bowing due to tensile stresses from deposited materials, leading to complications in subsequent processing steps like photolithography and potential scrapping of entire wafers, necessitating improved control over wafer bowing.
Innovation Solution
A method involving determining how wafer bow changes with temperature, applying a back side treatment to counteract this bowing by depositing layers such as silicon oxide and nitride on the back side of the wafer, and adjusting these layers' thickness and number to achieve neutral stress, thereby preventing wafer bowing during front side processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If materials are deposited on the front side of the wafer, then conductive traces and circuit elements are formed, but tensile stresses cause wafer bowing which complicates subsequent processing
Solution Approach 1:
The patent applies preliminary anti-action by depositing a back side treatment layer on the wafer back side before front side processing. This layer creates compressive stress that counteracts the tensile stress from front side deposition, preventing wafer bowing before it occurs. The system determines the required back side treatment properties by measuring wafer bow at multiple temperatures and calculating the compensating stress needed.
Solution Approach 2:
The patent utilizes parameter changes by varying the temperature during wafer bow measurement to determine how bow changes with temperature. This temperature-dependent characterization allows the system to calculate the optimal back side treatment layer properties (thickness, material composition) that will counteract the expected bow under processing conditions.
2Manufacturing precision
If excessive bowing occurs, then wafer processing becomes problematic, but preventing bowing requires complex temperature characterization and back side treatment
Solution Approach 1:
The system performs self-service by using the wafer itself as the test object. The same wafer structure that will undergo processing is used to measure bow characteristics, eliminating the need for separate test structures. The back side treatment is then applied to this characterized wafer, making the system self-calibrating and reducing external complexity.
Solution Approach 2:
The patent implements feedback by measuring actual wafer bow at multiple temperatures, using this measurement to calculate the required back side treatment properties, applying the treatment, and thereby controlling the bow. This closed-loop approach uses real data to drive the compensation process, reducing the need for complex predictive models.
3Manufacturing precision
If back side treatment layers are applied, then wafer bow is counteracted, but additional deposition steps and material layers are required
Solution Approach 1:
The patent merges operations by combining the back side treatment deposition with the front side processing sequence. The back side treatment layer is deposited as part of the overall fabrication process, and the wafer undergoes front side processing without removal. This integration reduces the number of separate steps and improves throughput while maintaining bow control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively maintains wafer flatness, preventing excessive bowing and ensuring successful subsequent processing steps by balancing stress on the wafer, reducing material consumption, and minimizing waste.
Implementation Method 1
deposited materials may give rise to tensile stresses at a surface of a semiconductor wafer. Such tensile stress can give rise to bowing of a semiconductor wafer
Implementation Method 2
Such deposition may involve formation of conductive traces, transistor gates, vias, circuit elements
Data Source
AI summary
A method of controlling wafer bow in an integrated circuit fabrication process may include characterizing the wafer bow in response to performing one or more first fabrication processes to an active side of an integrated circuit wafer. Determining one or more second fabrication processes, to be applied to a back side of the integrated circuit wafer, to bring the wafer bow to below a predetermined threshold based on the one or more first fabrication processes the method may additionally include performing the one or more second fabrication processes on the back side of the integrated circuit wafer.


