Wafer Bow Compensation for Lithography Overlay in Bonding

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Solution Overview

Problem

Semiconductor fabrication processes face challenges due to wafer distortion caused by material stress, leading to misalignment and overlay errors during photolithography, which affects the bonding of semiconductor elements.

Innovation Solution

A method is introduced to correct overlay errors by measuring wafer bow and shifting lithographic patterns based on bow measurements to align semiconductor elements accurately before bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If wafer bonding is performed without correction, then bonding process can be completed, but misalignment and overlay errors occur due to wafer distortion

Engineering Contradiction:
Improvealignment precisionVSAvoidmeasurement and correction system complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent measures wafer bow before photolithography and calculates corrected lithographic patterns in advance. By determining the bow measurement and computing compensation shifts before the actual patterning process, the system pre-corrects for expected distortion, ensuring accurate alignment without adding complexity to the bonding step itself.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system measures actual wafer bow using optical interferometry or capacitance sensing, then uses this feedback to calculate and apply corrections to the lithographic pattern positions. This closed-loop approach continuously adjusts for distortion based on real-time measurements, maintaining high alignment precision.

Inventive Principle:
Principle #23Feedback

2Manufacturing precision

If wafer bow is measured and patterns are shifted to correct overlay errors, then alignment precision improves, but process time increases due to additional measurement and calculation steps

Engineering Contradiction:
Improveoverlay accuracyVSAvoidfabrication cycle time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

Wafer bow measurement and pattern correction calculations are performed before photolithography begins. By completing these corrective actions in advance, the system avoids adding time during critical subsequent steps, streamlining the overall process while maintaining accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts lithographic pattern parameters (positions, shapes) based on measured wafer bow characteristics. By changing the pattern parameters in response to actual wafer conditions, the system achieves high overlay accuracy without requiring physical wafer manipulation or repositioning, saving time.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250226265A1Correcting of design and mask shape position due to die and wafer distortion for bonding
Publication Date: 2025.07.10 TOKYO ELECTRON LTD
  • US20250226265A1 patent drawing
  • US20250226265A1 patent drawing
  • US20250226265A1 patent drawing

AI summary

Aspects of the present disclosure provide a method for correcting an overlay error by shifting lithographic patterns to be formed on a wafer according to a bow measurement of the wafer. For example, the method can include receiving a first location at which one or more first semiconductor elements are to be formed on a first wafer, measuring the first wafer to identify a first bow measurement of the first wafer, calculating a second location that is shifted from the first location based on the first bow measurement, and forming the first semiconductor elements on the first wafer at the second location.