Wafer Bump Overlay Offset for IC Alignment
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Solution Overview
Problem
In integrated circuit packaging, the alignment of semiconductor chip bumps with substrate solder bumps is often disrupted by material stress, leading to position shifts and misalignment, which can cause stress on the chip and potentially result in open circuits.
Innovation Solution
The implementation of an overlay offset in the formation of metal bumps and under bump metallurgies, allowing for accurate alignment by adjusting the pitch, position, and orientation of bumps to match the distorted pitches caused by material stress, using a lithography stepper to apply the offset during the exposure of photo resist patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple layers of different materials are used in package substrate to achieve functional requirements, then the substrate can provide necessary electrical and mechanical functions, but material stress causes position shift of solder bumps leading to misalignment with chip bumps
Solution Approach 1:
The patent applies a preliminary position shift (overlay offset) to the chip bumps during the bump formation process. This offset is calculated based on the known position shift of solder bumps caused by material stress in the multi-layer substrate. By pre-adjusting the bump positions before bonding, the patent compensates for the anticipated misalignment, ensuring accurate alignment after bonding despite the substrate's material stress.
2Reliability
If accurate alignment of bumps with solder bumps is required to prevent open circuits, then manufacturing precision must be high, but this increases manufacturing complexity and cost
Solution Approach 1:
The patent incorporates the overlay offset directly into the bump formation process using lithography stepper adjustments. This preliminary action embeds the compensation mechanism within the existing manufacturing flow, avoiding the need for additional alignment steps or complex post-processing operations. The solution maintains high connection reliability while minimizing increases in manufacturing complexity.
3Ease of manufacture
If traditional alignment methods are used without overlay offset, then the manufacturing process is simpler, but misalignment occurs due to material stress causing open circuits
Solution Approach 1:
The patent modifies the positional parameters of the bump pattern during lithography exposure by applying an overlay offset. This parameter change adjusts the bump positions to account for the solder bump position shift caused by material stress. The modification is implemented through standard lithography stepper capabilities, maintaining ease of manufacture while significantly improving connection reliability by preventing misalignment-induced open circuits.
Data Source
AI summary
An integrated circuit structure includes a work piece selected from the group consisting of a semiconductor chip and a package substrate. The work piece includes a plurality of under bump metallurgies (UBMs) distributed on a major surface of the work piece; and a plurality of metal bumps, with each of the plurality of metal bumps directly over, and electrically connected to, one of the plurality of UBMs. The plurality of UBMs and the plurality of metal bumps are allocated with an overlay offset, with at least some of the plurality of UBMs being misaligned with the respective overlying ones of the plurality of metal bumps.