Wafer Butting Contact Structure for Reduced Thickness
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Solution Overview
Problem
Conventional metal-to-metal bonding methods for connecting wafers result in increased wafer thickness and longer wiring lengths, leading to power loss and increased fabrication time due to the need for separate conductive layer formation.
Innovation Solution
The method employs an oxide-to-oxide bonding process followed by electrical connection using through-silicon vias (TSVs) or butting contact holes, simplifying the process and reducing thickness and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal-to-metal bonding method is used to electrically connect wafers, then electrical connection between wafers is achieved, but wafer thickness increases and wiring length increases
Solution Approach 1:
The patent transitions from planar metal-to-metal bonding to vertical through-silicon via connections. By creating conductive paths through the wafer thickness dimension rather than along the surface, the electrical connection is achieved with minimal increase in overall wafer thickness, effectively moving the connection approach to a different spatial dimension.
Solution Approach 2:
The patent divides the electrical connection path into segments: through-silicon vias penetrating the first wafer, interconnect structures at the bonding interface, and additional vias through the second wafer. This segmentation allows each component to be optimized independently, reducing the total effective wiring length while maintaining reliable electrical connection.
2Reliability
If metal-to-metal bonding method is used to electrically connect wafers, then electrical connection is achieved, but power loss increases due to longer wiring
Solution Approach 1:
By transitioning from lateral surface connections to vertical through-silicon via connections, the patent dramatically reduces the effective current path length. The vertical dimension provides a direct, short path through the wafer thickness, minimizing resistive power loss compared to longer lateral routing paths.
3Reliability
If separate conductive layer formation process is performed during bonding, then electrical connection is achieved, but fabrication time increases
Solution Approach 1:
The patent merges the conductive layer formation process with the wafer bonding process itself. The through-silicon via structures are formed and prepared for bonding in an integrated sequence, eliminating separate post-bonding metallization steps. This consolidation reduces the total number of process steps and fabrication time while ensuring reliable electrical connection.
Solution Approach 2:
The patent performs preliminary formation of through-silicon via structures and conductive layers before the actual wafer bonding step. By preparing all electrical connection elements in advance, the bonding process itself becomes a simpler alignment and joining operation, reducing overall fabrication time and process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces wafer thickness, minimizes power loss, and streamlines the fabrication process, improving product yield and reducing errors.
Implementation Method 1
physically bonding the first and second wafers through an insulator-to-insulator bonding method
Data Source
AI summary
The present invention relates to a method for electrically connecting wafers, which physically bonds two wafers through an oxide-to-oxide bonding method and then electrically connects the two wafers through a butting contact structure. The wafers are physically bonded to each other through a relatively simple method, and then electrically connected to through TSVs or butting contact holes. Therefore, since the fabrication process may be simplified, a process error may be reduced, and the product yield may be improved.