Wafer Polishing with Cap Layer to Prevent Edge Short Circuits

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Solution Overview

Problem

Existing wafer processing methods face issues of dishing and edge consumption of the nitrided layer over the gate electrode, leading to potential short circuits and reduced yield rates, particularly in the edge and average regions of the wafer.

Innovation Solution

A method that omits the edge beam removal (EBR) process by depositing a first metallic layer, a cap layer, and a dielectric layer on the wafer, followed by polishing to form consumed portions in specific regions, ensuring the cap layer maintains thickness and prevents short circuits, with subsequent deposition of a second metallic layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the conventional EBR process is used to remove edge portions, then edge consumption is reduced, but dishing occurs and the nitrided layer thickness is compromised leading to short circuits

Engineering Contradiction:

Improveprevention of short circuitsVSAvoidnitrided layer thickness uniformity

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

A cap layer is deposited over the nitrided layer before the EBR process to protect it from excessive removal. The cap layer serves as a sacrificial layer that absorbs the edge beam removal action, preserving the underlying nitrided layer thickness and preventing short circuits while maintaining manufacturing precision.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The cap layer acts as an intermediary protective layer between the EBR process and the nitrided layer. It mediates the interaction by absorbing the harmful edge beam removal effects while allowing the nitrided layer to maintain its required thickness and electrical isolation function.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If polishing is performed to remove consumed portions, then edge consumption is controlled, but dishing occurs in the wafer surface

Engineering Contradiction:

Improveedge consumption controlVSAvoidwafer surface flatness

Core Design Contradiction:

Manufacturing precisionVSShape

Solution Approach 1:

The polishing process is optimized to apply different removal rates to different regions of the wafer. The cap layer design and polishing parameters are adjusted so that edge regions receive more removal to control edge consumption, while center regions receive less removal to maintain surface flatness and prevent dishing.

Inventive Principle:

Principle #3Local quality

3Reliability

If the nitrided layer is thinned at the edge to prevent short circuits, then electrical isolation is improved, but yield rate decreases due to increased defects in edge and average regions

Engineering Contradiction:

Improveelectrical isolationVSAvoidwafer yield rate

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The cap layer is deposited in advance to protect the nitrided layer during EBR. This preliminary protective action ensures that the nitrided layer maintains adequate thickness throughout the manufacturing process, preventing both short circuits and the formation of defects that would reduce yield rate in edge and average regions.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The cap layer, which could be seen as an additional process step increasing complexity, actually converts the harmful EBR effect into a beneficial protective mechanism. By allowing controlled removal of the cap layer at edges while preserving the nitrided layer, it simultaneously improves electrical isolation reliability and maintains high yield rates.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improves yield rates by 6-8% in the edge region and 1.6-1.8% in the average region, reducing dishing and edge consumption, and maintaining the nitrided layer thickness to prevent short circuits.

Implementation Method 1

A first metallic layer is deposited on the wafer. A cap layer is deposited on the first metallic layer.

Methodology Applied

Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

A polishing process is performed to the dielectric layer, such that a consumed portion of the cap layer and a consumed portion of the first metallic layer are formed in the second region of the wafer.

Methodology Applied

Scientific EffectAbrasion: Abrasion

Data Source

PatentUS20260011566A1Method for processing a wafer

Publication Date: 2026.01.08 NAN YA TECH

AI summary

A method for processing a wafer is provided. The method includes providing a wafer, in which the wafer has a first region and a second region, and the second region is between an edge of the wafer and the first region; depositing a first metallic layer on the wafer; depositing a cap layer on the first metallic layer; disposing a dielectric layer on the cap layer, in which the dielectric layer covers a sidewall of the first metallic layer and a sidewall of the cap layer; performing a polishing process to the dielectric layer, such that a consumed portion of the cap layer and a consumed portion of the first metallic layer is formed in the second region of the wafer.