Wafer Carrier Support Layout for Fragile TSV Topography
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Solution Overview
Problem
Existing wafer carriers are incompatible with wafers that have fragile structures and topography, particularly those undergoing high-temperature processes or with through-silicon vias, as they apply excessive stress or are not compatible with the wafer's geometry, risking damage or breakage during handling and fabrication.
Innovation Solution
A carrier base with alignment features and support structures that contact the wafer between fabricated regions, using a combination of hard clamping and soft vacuum to secure the wafer, with recesses and cavities to accommodate topography, and materials like silicon or ceramic to match the wafer's properties, ensuring minimal stress and compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a flat carrier is used for wafer-level integration, then the wafer can be secured during assembly steps, but the carrier applies excessive stress to fragile structures and is incompatible with wafer topography, risking damage or breakage
Solution Approach 1:
The carrier base incorporates recesses and cavities that create locally adapted contact regions. These recesses are positioned to contact the wafer at specific locations between fabricated structure regions, providing local support that accommodates the wafer's topography while avoiding stress concentration on fragile structures.
Solution Approach 2:
The invention transitions from a flat, two-dimensional carrier surface to a three-dimensional surface with recesses and cavities. This dimensional change allows the carrier to conform to the wafer's topography, creating contact points that avoid fabricated structure regions while providing adequate support.
2Ease of manufacture
If thick and compliant backside grinding tape or hot wax mounting methods are used, then the wafer can be mounted during processing, but these methods require excessive force and effort for debonding, making them incompatible with fragile wafers
Solution Approach 1:
The invention replaces mechanical bonding methods (grinding tape, hot wax) with a vacuum-based securing system. The carrier base includes a vacuum source that creates a partial vacuum within cavities to hold the wafer in place, eliminating the need for strong adhesive bonds that would require excessive force to break during debonding.
3Temperature
If typical carriers are used for high temperature processes, then the wafer can be processed, but the carrier cannot accommodate wafer topography on the opposite side, causing stress and potential damage
Solution Approach 1:
The carrier base features recesses and cavities positioned to contact the wafer at specific locations between fabricated structure regions. This local adaptation allows the carrier to accommodate the wafer's topography on the opposite side while maintaining structural integrity during high-temperature processing.
Solution Approach 2:
The carrier uses a compliant layer that can deform and adapt to the wafer's topography during high-temperature processes. This compliant layer acts as a stress-absorbing interface that protects the fragile fabricated structures while withstanding thermal processing conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables secure handling and fabrication of fragile wafers with through-silicon vias, reducing the risk of damage and allowing for precise alignment and stress-free processing, facilitating 3D integration and heterogeneous integration while maintaining signal integrity.
Implementation Method 1
the carrier base comprising one or more alignment features for aligning the wafer to the carrier base
Implementation Method 2
three or more of the support structures are each configured to contact the first side of the wafer when the wafer is secured to the carrier base, and arranged on the carrier base to contact the first side of the wafer at a location on the first side of the wafer that is between at least two of the plurality of fabricated structure regions
Implementation Method 3
using a combination of hard clamping and soft vacuum to secure the wafer
Implementation Method 4
with recesses and cavities to accommodate topography
Implementation Method 5
materials like silicon or ceramic to match the wafer's properties, ensuring minimal stress and compatibility
Data Source
AI summary
An apparatus for securing a wafer, the wafer having a first side comprising a plurality of fabricated structure regions and a second side that has at least one region that is exposed for fabrication when the wafer is secured, comprises: a carrier base configured to receive the wafer, the carrier base comprising one or more alignment features for aligning the wafer to the carrier base; and a plurality of support structures arranged on the carrier base. Three or more of the support structures are each configured to contact the first side of the wafer when the wafer is secured to the carrier base, and arranged on the carrier base to contact the first side of the wafer at a location on the first side of the wafer that is between at least two of the plurality of fabricated structure regions.