Wafer Cassette Lift Pin Layout for Backside Deposition Prevention
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Solution Overview
Problem
Current batch processing chambers for semiconductor wafers deposit films on both the front and back sides, which is undesirable for further processing and reduces production yield.
Innovation Solution
A batch processing chamber design with a wafer cassette assembly and lift pin assembly that minimizes backside deposition by using a unique lift pin mechanism to handle wafers, allowing gas flow only across the front side, and includes a thermal mass for faster heating and improved film quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gas is injected into the processing chamber to flow across the surface of the wafers for batch deposition, then film deposition on the front side is achieved, but film deposition on the back side also occurs which is undesirable
Solution Approach 1:
The wafer support structure is segmented into multiple discrete supports positioned at different heights, allowing selective exposure of wafer surfaces to the gas flow. Each wafer support can be independently positioned to control which surface (front or back) is exposed to the deposition environment, enabling precise control over deposition location while maintaining batch processing capability.
Solution Approach 2:
The patent introduces vertical stacking of wafers on support columns, adding a height dimension to the traditional planar wafer arrangement. By positioning wafers at different heights and orientations, the system controls gas flow exposure to specific surfaces, preventing unwanted backside deposition while maintaining efficient batch processing throughput.
2Productivity
If multiple wafers are processed simultaneously in batch to increase production yield, then throughput is improved, but backside deposition occurs on all wafers reducing yield
Solution Approach 1:
The gas flow distribution is optimized to create local quality differences across the batch of wafers. By controlling the flow patterns and wafer positioning, the system ensures that only the intended surfaces (front or back) of each wafer are exposed to the deposition environment, while other surfaces remain protected. This maintains high processing quality for all wafers in the batch while preserving improved throughput.
3Productivity
If wafers are stacked vertically on support columns for batch processing, then space utilization and throughput are improved, but gas flow distribution and deposition uniformity become more difficult to control
Solution Approach 1:
The wafer support columns are designed with adjustable positioning capabilities, allowing the system to dynamically optimize wafer positions and orientations during different processing steps. This dynamic adjustment ensures uniform gas flow distribution and consistent deposition across all wafers in the vertical stack, while maintaining high throughput from the compact vertical arrangement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents backside deposition, reduces process cycle time, and enhances film quality and throughput by ensuring uniform deposition on the front side while maintaining rapid wafer heating and efficient handling.
Implementation Method 1
A lift pin is extended through the opening in the wafer support and contacts the wafer. The lift pin is raised to lift the wafer off of the wafer support.
Implementation Method 2
A batch processing chamber design with a wafer cassette assembly and lift pin assembly that minimizes backside deposition by using a unique lift pin mechanism to handle wafers, allowing gas flow only across the front side
Data Source
AI summary
Processing chambers having a chamber body with a wafer cassette assembly and at least one lift pin assembly are described. The wafer cassette assembly has at least two support columns configured to hold a plurality of wafer supports spaced along a height of the support columns. The lift pin assemblies have a plurality of lift pins arranged so that each of the plurality of wafer supports comprises at least three lift pins.