Wafer Processing Apparatus CD Variation Compensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing critical dimension (CD) variations across wafers in the semiconductor industry lead to fluctuations in transistor performance characteristics, resulting in poor device performance and low yield, due to the scaling down of process geometries and increased complexity in maintaining process variations.
Innovation Solution
A wafer processing apparatus and method that utilizes a 3D model to modify surface features in the Z-direction based on X-CD and Y-CD variations, employing optical techniques like scatterometry and ellipsometry to analyze and compensate for non-uniformities by varying material properties along the Z-direction at different X-Y locations, using etch and deposition tools for precise adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down process geometries to increase functional density, then production efficiency increases and costs decrease, but critical dimension variations across the wafer increase
Solution Approach 1:
The patent applies local quality by modifying processing parameters at different locations across the wafer surface. The system maps CD variations across the wafer and applies location-specific compensation adjustments to deposition and etch processes, ensuring that each region receives tailored processing conditions to achieve uniform CD control despite scaling challenges
Solution Approach 2:
The patent introduces a spatial dimension to process control by creating a 2D map of CD variations across the wafer surface and using this spatial information to adjust processing parameters. This transforms the control approach from uniform across-wafer processing to location-specific processing, adding a spatial dimension to the manufacturing process
2Quantity of substance
If scaling down process geometries to increase functional density, then transistor density increases, but device performance characteristics fluctuate
Solution Approach 1:
The patent implements feedback control by measuring CD variations across the wafer surface, mapping these variations, and using the mapped information to adjust subsequent processing parameters. This closed-loop feedback system continuously monitors and corrects CD deviations, ensuring consistent device performance characteristics across the wafer despite scaling to higher transistor densities
3Manufacturing precision
If increasing inspection and measurement to control feature dimensions, then CD control improves, but process complexity increases
Solution Approach 1:
The patent applies preliminary action by performing CD measurements and creating variation maps before final processing steps. This advance mapping allows the system to pre-calculate compensation adjustments and apply them in subsequent processing, preventing CD deviations rather than merely detecting them, thereby reducing the need for complex real-time control systems
Data Source
AI summary
An apparatus of a wafer processing apparatus includes at least one memory and logic, at least a portion of which is implemented in circuitry of the wafer processing apparatus including at least one processor coupled to the at least one memory. The logic may provide a 3D model of a surface of a wafer, the wafer defining a wafer plane; and modify a surface feature in a Z-direction along the surface of the wafer based on at least one of: an X-critical dimension (CD) extending along an X-direction of the wafer plane, and a Y-CD extending along a Y direction of the wafer plane.